Abstract: A battery cell includes a shell, an end cover, an electrode assembly, and a current collector component. The shell has an opening, and the inner surface of the shell is provided with a first limit part in a protruding manner. The end cover covers the opening. The electrode assembly and the end cover are respectively located on both sides of the first limit part, and the electrode assembly has a tab on the side facing the end cover. The current collector component includes a body part and a connecting part, and the connecting part is connected to the first limit part. The body part includes a first welding region and a second welding region, the first welding region is located on the periphery of the second welding region, the first welding region and the second welding region are separated by the connection position between the connecting part and the body part.

Abstract: A driving substrate, a micro LED transfer device and a micro LED transfer method are provided. A side surface of the driving substrate is arranged with a binding metal layer, a positioning layer is arranged around the binding metal layer, and a width of the positioning layer at a position away from the driving substrate is less than that a width at a position close to the driving substrate.

Abstract: A battery cell includes a shell, an end cover, an electrode assembly, and a current collector component. The shell has an opening, and the inner surface of the shell is provided with a first limit part in a protruding manner. The end cover covers the opening. The electrode assembly and the end cover are respectively located on both sides of the first limit part, and the electrode assembly has a tab on the side facing the end cover. The current collector component includes a body part and a connecting part, and the connecting part is connected to the first limit part. The body part includes a first welding region and a second welding region, the first welding region is located on the periphery of the second welding region, the first welding region and the second welding region are separated by the connection position between the connecting part and the body part.

Abstract: A LED chip transfer method comprises: providing a driving substrate having at least one set of binding points, the set of binding points comprising a first and second binding points; forming a compensation layer covering the first and second binding points; providing a chip substrate comprising a substrate and chips; performing a first alignment treatment to form a first groove and a second groove on the compensation layer; forming a first and second via holes spaced from each other by the first groove and the second groove, forming a first transfer electrode and a second transfer electrode disconnected from each other on the compensation layer, inserting the first pin and the second groove into the first groove and the second groove to bind with the first transfer electrode and the second transfer electrode; and stripping the substrate from the chip.

Abstract: A system controller determines a to-be-collected first logical chunk group. The first logical chunk group includes a first data logical chunk located in a first solid state disk of the plurality of solid state disks. Valid data is stored in a first logical address in the first logical chunk group, and there is a correspondence between the first logical address and an actual address in which the valid data is stored. The system controller creates a second logical chunk group. At least one second data logical chunk in the second logical chunk group is distributed in the solid state disk in which the first data logical chunk storing a valid data is located in order to ensure that the valid data is migrated from the first logical chunk group to the second logical chunk group, but an actual address of the valid data remains unchanged.

Abstract: Apparatuses, systems, and methods for providing maximum transmit power control when utilizing multiple radio access technologies. For example, a wireless communication device comprising two cellular radios may intend to transmit on the first radio, while concurrently transmitting on the second radio. To ensure compliance with a maximum transmit power limitation, the device may determine an allowed transmit power level of the first radio, representing a difference between the maximum transmit power limitation and the current transmit power level being transmitted by the second radio. The device may also determine a threshold power level for a communication by the first radio. If the allowed transmit power level meets the threshold power level, then the device may transmit the first communication having a power level between the threshold power level and the allowed transmit power level. Otherwise, the device may forego transmission of the first communication.

Abstract: A growth substrate and the display panel include a substrate, including chip growth regions arranged at intervals and in an array and a non-growth region located among chip growth regions. The growth substrate includes a refraction structure disposed on the substrate. An orthographic projection of the refraction structure on the substrate covers the non-growth region without overlapping with at least parts of the chip growth regions. The refraction structure is configured to refract light corresponding to the non-growth region to positions corresponding to the chip growth regions. The substrate has a first surface and a second surface and light emitting chips are grown in the chip growth regions of the first surface. The refraction structure is disposed on the second surface, an orthographic projection on the substrate covers the non-growth region, and one side, away from the substrate, of the refraction structure is a light incident side.

Abstract: A display device includes a substrate, a display unit, a binding unit, and an encapsulation layer. The substrate includes an effective display region and a non-display region adjacent to the effective display region, and includes a silicon-containing compound material. The display unit is arranged in the effective display region. The binding unit is arranged in the non-display region and includes a binding portion and signal connection lines. Two ends of the signal connection line are connected to the display unit and the binding portion, respectively. The encapsulation layer wraps the display unit and a part of the signal connection lines The encapsulation layer covers a portion of each of the plurality of signal connection lines, at least a portion of each of the plurality of signal connection lines disposed inside a region covered by the encapsulation layer is configured as a heavily doped semiconductor connection line.

Abstract: A display panel includes a drive backplane and a plurality of light-emitting chips arranged on the drive backplane. Each of the light-emitting chips includes an N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer arranged on the undoped semiconductor layer in sequence and an undoped semiconductor layer. The undoped semiconductor layer is provided with a conductive via. The light-emitting chip further includes a conductive pattern portion, a part of the conductive pattern portion is located in the conductive via and is in contact with the N-type semiconductor layer, and another part of the conductive pattern portion protrudes from the conductive via and is connected to the drive backplane.

Abstract: A display panel and a display device are provided in the disclosure. The display panel includes a carrier substrate, multiple emitting units disposed on the carrier substrate, and multiple light absorbing and reflecting assemblies. The multiple light absorbing and reflecting assemblies are disposed in correspondence with the multiple light emitting units and each of the multiple light absorbing and reflecting assemblies defines an opening, and where the light absorbing and reflecting assembly is configured to reflect at least part of light emitted by the light emitting unit to radiate through the opening, and to absorb external ambient light.

Abstract: A pixel structure includes: a gate electrode disposed on a base substrate; a gate insulation layer covering the gate electrode; a source electrode, an active region, a drain electrode, a first doped region and a secondary electrode metal layer disposed on an upper surface of the gate insulation layer sequentially; two second doped regions at two ends of an upper surface of the active region; and a passivation layer covering source electrode, a portion of the active region exposed to the second doped regions, the second doped regions, the drain electrode, the first doped region and the secondary electrode metal layer. The passivation layer is provided with a primary pixel electrode and a secondary pixel electrode disposed thereon, the primary pixel electrode is connected to the drain electrode, and the secondary pixel electrode is connected to the secondary electrode metal layer.

Abstract: A display structure comprises pixel areas. At least one side of each of the pixel areas is provided with a viewing angle adjustment area. Each of the pixel areas is provided with light emitting part for emitting light, the viewing angle adjusting part includes a light shielding part and an adjusting electrode. The light shielding part has a narrow viewing angle position for shielding light from light emitting part and a wide viewing angle position for avoiding light from the light emitting part. The adjusting electrode is disposed corresponding to the light shielding part. The adjusting electrode forms an electric field, to drive the light shielding part is driven by the electric to move between the narrow viewing angle position and the wide viewing angle position.

Abstract: A pixel driving circuit and a display device are provided. The pixel driving circuit is configured to drive a pixel unit to operate, and the pixel driving circuit includes a first compensation sub-circuit and a second compensation sub-circuit. The first compensation sub-circuit is configured to compensate a voltage of an anode of the pixel unit according to a reference signal and a data signal, and the second compensation sub-circuit is configured to compensate a leakage current generated by at least one transistor in the first compensation sub-circuit according to a leakage current generated by the second compensation sub-circuit.

Abstract: A display panel, a manufacturing method of the display panel, and a display device are disclosed. The display panel includes a first substrate and a second substrate. The first substrate includes a first base, a light-shielding layer disposed on the first base, and a color filter layer disposed on the first base, and a common electrode layer disposed on the light-shielding layer and the color filter layer. The common electrode layer is provided with an opening at a position opposite to the color filter layer.

Abstract: A display panel, a manufacturing method of the display panel, and a display device are disclosed. The display panel includes a first substrate and a second substrate. The first substrate includes a first base, a light-shielding layer disposed on the first base, and a color filter layer disposed on the first base, and a common electrode layer disposed on the light-shielding layer and the color filter layer. The common electrode layer is provided with an opening at a position opposite to the color filter layer.

Abstract: The present invention provides a chip ESD protection circuit, includes an integrated circuit layer and a conductive layer. A first ground bonding pad that is connected to a first ground wire of a first power domain is disposed on each of the first power domain and a second power domain in the integrated circuit layer. The first ground bonding pads are bonded to the conductive layer. A second power clamping unit is disposed on the second power domain. A first end of the second power clamping unit is connected to a second power wire of the second power domain, and a second end thereof is connected to the first ground wire or a second ground wire of the second power domain. According to the chip ESD protection circuit, the ESD protection capability of a chip can be improved. The occupied area of the chip is reduced.

Abstract: A method is provided for deep tissue imaging using multi-photon excitation of a fluorescent agent. The fluorescent agent is irradiated with an ultrafast laser to produce an excited singlet state (Sn) which subsequently undergoes non-radiative relaxation to a first singlet state (S1). The S1 state undergoes fluorescence to the ground state S0 to produce an emission wavelength. Both the excitation and emission wavelengths are within the near infrared optical window, thereby permitting deep tissue penetration for both the incoming and outgoing signals.

Abstract: A rectal near infrared (NIR) scanning polarization imaging system uses NIR Photonic Prostatoscopy Analyzer (NIRPPA) for prostate cancer detection using light. The NIRPPA consists of a portable rectal NIR scanning polarization imaging unit and an optical fiber-based rectal probe capable of recording sets of 2D images of a prostate through rectum at different wavelengths and depths and obtaining a three dimensional (3D) image of the prostate and 3D locations of abnormal tissue inside the prostate. Diode lasers/light emission diodes (LEDs) with selected emitting wavelengths are used in the NIR spectral range from 650 nm to 2,400 nm corresponding to the four tissue optical windows (#I, 650 nm-950 nm; #II, 1,100 nm-1,350 nm; #III, 1,600 nm-1,870 nm; and #IV, 2,100 nm-2,300 nm). The fingerprint absorptions of water (H2O), Oxyhemoglobin (HbO2) and deoxyhemoglobin (Hb) in the prostate are used as native biomarkers for prostate cancer detection.

Abstract: The present invention provides a chip ESD protection circuit, includes an integrated circuit layer and a conductive layer. A first ground bonding pad that is connected to a first ground wire of a first power domain is disposed on each of the first power domain and a second power domain in the integrated circuit layer. The first ground bonding pads are bonded to the conductive layer. A second power clamping unit is disposed on the second power domain. A first end of the second power clamping unit is connected to a second power wire of the second power domain, and a second end thereof is connected to the first ground wire or a second ground wire of the second power domain. According to the chip ESD protection circuit, the ESD protection capability of a chip can be improved. The occupied area of the chip is reduced.

Abstract: The present disclosure is directed to a system for controlling a plurality of managed devices. The system may involve a manageability services module adapted to facilitate communication between the plurality of managed devices and a central user located remotely from the plurality of managed devices. The system may also involve a manageability engine module that communicates with the manageability services module. The manageability engine module may have an element library storing parameters associated with the plurality of managed devices, and may be configured to perform a number of useful operations such as: facilitating communication between the managed devices and the manageability services module; discovering a new managed device; and collecting, aggregating and providing real time analytics on the data collected from the managed devices. A database may be used to store data collected by the manageability engine module.