Abstract: A thin film transistor includes a semiconductor layer, a first gate electrode disposed at one side of the semiconductor layer, a first gate insulating layer disposed between the first gate electrode and the semiconductor layer, a second gate electrode and a third gate electrode disposed at another side of the semiconductor layer, and a second gate insulating layer. The second gate electrode is separated from the third gate electrode. The second gate insulating layer is disposed between the second and third gate electrodes and the semiconductor layer. An orthogonal projection of the first gate electrode on the semiconductor layer is partially overlapped with an orthogonal projection of the second gate electrode on the semiconductor layer. The orthogonal projection of the first gate electrode on the semiconductor layer is partially overlapped with an orthogonal projection of the third gate electrode on the semiconductor layer.

Abstract: A semiconductor device, including a substrate, a semiconductor structure, a first gate dielectric layer, a first gate, a source, and a drain, is provided. The semiconductor structure includes a first metal oxide layer and a second metal oxide layer. The second metal oxide layer covers a top surface and a sidewall of the first metal oxide layer. The second metal oxide layer has a stepped structure at the sidewall of the first metal oxide layer. A carrier mobility of the first metal oxide layer is greater than a carrier mobility of a channel region of the second metal oxide layer. A thickness of the second metal oxide layer is greater than or equal to a thickness of the first metal oxide layer. A difference between a width of the first gate and a width of the first metal oxide layer is less than 0.5 ?m.

Abstract: A semiconductor device includes a substrate, a first thin-film transistor, and a second thin-film transistor. The first and second thin-film transistors are disposed on the substrate. The first thin-film transistor includes stacked first and second metal oxide layers. An oxygen concentration of the first metal oxide layer is less than an oxygen concentration of the second metal oxide layer, and a thickness of the second metal oxide layer is less than a thickness of the first metal oxide layer. A two-dimensional electron gas is located at an interface between the first and second metal oxide layers. The second thin-film transistor is electrically connected to the first thin-film transistor. The second thin-film transistor includes a third metal oxide layer. The second and third metal oxide layers belong to a same patterned layer.

Abstract: A semiconductor device, including a first gate, a second gate, a third gate, a first semiconductor layer, a second semiconductor layer, a source, and a drain, is provided. The first semiconductor layer is located between the first gate and the second gate. The second gate is located between the first semiconductor layer and the second semiconductor layer. The second semiconductor layer is located between the second gate and the third gate. The source is electrically connected to the first semiconductor layer and the second semiconductor layer. The drain is electrically connected to the first semiconductor layer and the second semiconductor layer.

Abstract: An active device substrate includes a substrate, a first semiconductor device and a second semiconductor device. The first semiconductor device and the second semiconductor device are disposed above the substrate. The first semiconductor device includes a first gate, a first semiconductor layer, a first source and a first drain. A first gate dielectric structure is sandwiched between the first gate and the first semiconductor layer. The first gate dielectric structure includes a stack of a portion of a gate dielectric layer and a portion of a ferroelectric material layer. The second semiconductor device is electrically connected to the first semiconductor device and includes a second gate, a second semiconductor layer, a second source and a second drain. Another part of the ferroelectric material layer is sandwiched between the second gate and the second semiconductor layer.

Abstract: A thin film transistor includes a semiconductor layer, a first gate electrode disposed at one side of the semiconductor layer, a first gate insulating layer disposed between the first gate electrode and the semiconductor layer, a second gate electrode and a third gate electrode disposed at another side of the semiconductor layer, and a second gate insulating layer. The second gate electrode is separated from the third gate electrode. The second gate insulating layer is disposed between the second and third gate electrodes and the semiconductor layer. An orthogonal projection of the first gate electrode on the semiconductor layer is partially overlapped with an orthogonal projection of the second gate electrode on the semiconductor layer. The orthogonal projection of the first gate electrode on the semiconductor layer is partially overlapped with an orthogonal projection of the third gate electrode on the semiconductor layer.

Abstract: An active element and a manufacturing method thereof are provided. The active element includes a substrate, a switching bottom gate and a driving bottom gate disposed on the substrate, a first gate insulating layer disposed on the substrate and covering the switching bottom gate and the driving bottom gate, a switching channel and a driving channel disposed on the first gate insulating layer, a second gate insulating layer disposed on the first gate insulating layer and covering the switching channel and the driving channel, and a switching top gate and a driving top gate disposed on the second gate insulating layer. The driving channel has a low potential end electrically connected to the driving bottom gate. A thickness of the second gate insulating layer is greater than a thickness of the first gate insulating layer. The switching top gate is electrically connected to the switching bottom gate.

Abstract: A memory structure includes a control unit and a memory unit electrically connected to the control unit. The control unit includes a source and a drain; an active layer in contact with a portion of the source and a portion of the drain; a gate layer; and a gate insulation layer disposed between the active layer and the gate layer. The memory unit includes a bottom electrode layer; a top electrode layer; and a resistive switching layer interposed between the bottom electrode layer and the top electrode layer, which the resistive switching layer and the active layer are formed of aluminum zinc tin oxide (AZTO).

Abstract: A memory structure includes a control unit and a memory unit electrically connected to the control unit. The control unit includes a source and a drain; an active layer in contact with a portion of the source and a portion of the drain; a gate layer; and a gate insulation layer disposed between the active layer and the gate layer. The memory unit includes a bottom electrode layer; a top electrode layer; and a resistive switching layer interposed between the bottom electrode layer and the top electrode layer, which the resistive switching layer and the active layer are formed of aluminum zinc tin oxide (AZTO).

Abstract: A memory structure includes a control unit and a memory unit electrically connected to the control unit. The control unit includes a source and a drain; an active layer in contact with a portion of the source and a portion of the drain; a gate layer; and a gate insulation layer disposed between the active layer and the gate layer. The memory unit includes a bottom electrode layer; a top electrode layer; and a resistive switching layer interposed between the bottom electrode layer and the top electrode layer, which the resistive switching layer and the active layer are formed of aluminum zinc tin oxide (AZTO).

Abstract: A resistive random access memory (RRAM) device and operating method are disclosed herein. The RRAM device includes at least one RRAM cell and a control circuit. The RRAM cell includes a bottom electrode, an amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) layer, a Ti layer and a top electrode. The a-IGZO layer is disposed on the bottom layer. The Ti layer is disposed on the a-IGZO layer. The top electrode is disposed on the Ti layer. The control circuit is configured to provide at least one electrical signal to the RRAM cell, so as to change the resistance value of the RRAM cell.

Abstract: A resistive random access memory (RRAM) device and operating method are disclosed herein. The RRAM device includes at least one RRAM cell and a control circuit. The RRAM cell includes a bottom electrode, an amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) layer, a Ti layer and a top electrode. The a-IGZO layer is disposed on the bottom layer. The Ti layer is disposed on the a-IGZO layer. The top electrode is disposed on the Ti layer. The control circuit is configured to provide at least one electrical signal to the RRAM cell, so as to change the resistance value of the RRAM cell.

Abstract: A manufacturing method for manufacturing a flexible non-volatile memory is provided. The manufacturing method comprises the steps outlined below. A flexible substrate is provided. A planarization layer is formed on the flexible substrate. A metal bottom electrode layer is deposited on the planarization layer. A mask is formed to define a plurality of patterns. An AZTO layer having a plurality of electrically independent AZTO cells is deposited on the metal bottom electrode layer corresponding to the patterns. A top electrode layer is deposited on the AZTO layer corresponding to the AZTO cells to form a plurality of non-volatile memory cells.

Abstract: A manufacturing method for manufacturing a flexible non-volatile memory is provided. The manufacturing method comprises the steps outlined below. A flexible substrate is provided. A planarization layer is formed on the flexible substrate. A metal bottom electrode layer is deposited on the planarization layer. A mask is formed to define a plurality of patterns. An AZTO layer having a plurality of electrically independent AZTO cells is deposited on the metal bottom electrode layer corresponding to the patterns. A top electrode layer is deposited on the AZTO layer corresponding to the AZTO cells to form a plurality of non-volatile memory cells.