Abstract: A processing method includes acquiring, by a first service node of a first blockchain, a cross-chain transfer request, the cross-chain transfer request including a virtual resource value, a first resource transfer-out address on the first blockchain, and a first resource transfer-in address on a second blockchain. The cross-chain transfer request is used by a second service node of the second blockchain to lock a first virtual resource of the virtual resource value in the second blockchain. The method further includes performing resource transfer-out processing on a second virtual resource associated with the virtual resource value in the first resource transfer-out address in response to a determination that the second service node locked the first virtual resource successfully. The method further includes transferring the first virtual resource to the first resource transfer-in address in the second blockchain in response to a determination that the second virtual resource was transferred out.

Abstract: A data processing method performed by a first device includes: generating, in response to first service data satisfying a data uploading condition, a first bit array corresponding to the first service data; encrypting the first bit array through a data key to obtain a ciphertext bit array, the data key being generated by a second device in a data intersection application run in a trusted execution environment of the second device; and transmitting the ciphertext bit array to a blockchain node for forwarding to a second device, for the second device to decrypt, in the data intersection application through the data key, the ciphertext bit array to obtain the first bit array.

Abstract: The present invention discloses a bi-mode insulated gate transistor, belonging to the technical filed of IGBTs. The bi-mode insulated gate transistor includes a reverse conducting region and a pilot region, wherein the reverse conducting region and the pilot region each include P+ collector regions, a drift region and a MOS cell region, the drift regions are disposed over the P+ collector regions, and the MOS cell regions are disposed over the drift regions; the reverse conducting region further includes N+ collector regions, and the N+ collector regions and the P+ collector regions are distributed alternatively; the pilot region further includes a separation region or a low-doped region, the separation region isolates the P+ collector regions of the pilot region from the P+ collector regions and the N+ collector regions of the reverse conducting region, and the low doped region is disposed over the P+ collector regions of the pilot region.

Abstract: An ITC-IGBT and a manufacturing method therefor. The method comprises: providing a heavily doped substrate, forming a GexSi1-x/Si multi-quantum well strained super lattice layer on the surface of the heavily doped substrate, and forming a lightly doped layer on the surface of the GexSi1-x/Si multi-quantum well strained super lattice layer. The GexSi1-x/Si multi-quantum well strained super lattice layer is formed on the surface of the heavily doped substrate through one step, simplifying the production process of the ITC-IGBT.

Abstract: A TI-IGBT, comprising a first semiconductor substrate, a second semiconductor substrate, and a first doped layer; a short circuit region and a collector region disposed in parallel are formed in the first semiconductor substrate; the short circuit region and the collector region have different doping types; the second semiconductor substrate is located on the upper surface of the first semiconductor substrate, and has the same doping type with the short circuit region; the first doped layer is located between the first semiconductor substrate and the second semiconductor substrate, and covers at least the collector region; the first doped layer has the same doping type with the second semiconductor substrate, and has a doping concentration smaller than that of the second semiconductor substrate.

Abstract: A TI-IGBT, comprising a first semiconductor substrate, a second semiconductor substrate, and a first doped layer; a short circuit region and a collector region disposed in parallel are formed in the first semiconductor substrate; the short circuit region and the collector region have different doping types; the second semiconductor substrate is located on the upper surface of the first semiconductor substrate, and has the same doping type with the short circuit region; the first doped layer is located between the first semiconductor substrate and the second semiconductor substrate, and covers at least the collector region; the first doped layer has the same doping type with the second semiconductor substrate, and has a doping concentration smaller than that of the second semiconductor substrate.

Abstract: An ITC-IGBT and a manufacturing method therefor. The method comprises: providing a heavily doped substrate, forming a GexSi1-x/Si multi-quantum well strained super lattice layer on the surface of the heavily doped substrate, and forming a lightly doped layer on the surface of the GexSi1-x/Si multi-quantum well strained super lattice layer. The GexSi1-x/Si multi-quantum well strained super lattice layer is formed on the surface of the heavily doped substrate through one step, simplifying the production process of the ITC-IGBT.