Patents by Inventor Yanhua Yi
Yanhua Yi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11966677Abstract: A method is disclosed. The method includes computing a time delay for each path of a plurality of paths of a circuit design and determining a commonality score based on a number of segments that are common between the plurality of paths of the circuit design. The method further includes determining a criticality score based on the time delay for each path of the plurality of paths of the circuit design. The method further includes generating a graphical representation of the plurality of paths, wherein a first dimension of the graphical representation corresponds to the commonality score and wherein a second dimension of the graphical representation corresponds to the criticality score. The method further includes providing the graphical representation of the plurality of paths in a graphical user interface (GUI) to represent the plurality of paths in the circuit design.Type: GrantFiled: August 31, 2021Date of Patent: April 23, 2024Assignee: SYNOPSYS, INC.Inventors: Melvyn Goveas, Ribhu Mittal, Wen-Chi Feng, Yanhua Yi
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Publication number: 20240094290Abstract: A method or system for estimating delays in design under tests (DUTs) using machine learning. The system accesses multiple DUTs, each comprising various logic blocks. For each DUT, a combinatorial path is identified, connecting one or more logic blocks. A feature vector is generated, including values of orthogonal features representing the combinatorial path's characteristics. Each DUT is compiled for emulation, and the delay of its combinatorial path is measured. These measured delays, along with the corresponding feature vectors, are used to train a machine learning delay model. The trained model is designed to receive a combinatorial path of a DUT as input and generate an estimated wire delay as output. This approach leverages machine learning to predict delays in electronic designs, improving the efficiency and accuracy of delay estimations in complex circuits.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Inventors: Yanhua Yi, Yu Yang, Jiajun Fan, Vinod Kumar Nakkala, Vijay Sundaresan, Jianfeng Huang
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Patent number: 11860227Abstract: A delay estimation system estimates a delay of a DUT for an emulation system. The delay estimation system receives logic blocks of the DUT and a combinatorial path connecting one or more of the logic blocks. The system applies a delay model to a feature vector representing the combinatorial path, where the delay model can determine a delay of the combinatorial path. The delay model may be a machine learning model. The system generates a timing graph using the determined delay and provides the timing graph to a compiler to perform placement and routing of the DUT.Type: GrantFiled: December 10, 2021Date of Patent: January 2, 2024Assignee: Synopsys, Inc.Inventors: Yanhua Yi, Yu Yang, Jiajun Fan, Vinod Kumar Nakkala, Vijay Sundaresan, Jianfeng Huang
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Publication number: 20220187367Abstract: A delay estimation system estimates a delay of a DUT for an emulation system. The delay estimation system receives logic blocks of the DUT and a combinatorial path connecting one or more of the logic blocks. The system applies a delay model to a feature vector representing the combinatorial path, where the delay model can determine a delay of the combinatorial path. The delay model may be a machine learning model. The system generates a timing graph using the determined delay and provides the timing graph to a compiler to perform placement and routing of the DUT.Type: ApplicationFiled: December 10, 2021Publication date: June 16, 2022Inventors: Yanhua Yi, Yu Yang, Jiajun Fan, Vinod Kumar Nakkala, Vijay Sundaresan, Jianfeng Huang
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Patent number: 9672307Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes determining clock resources in a design identifying operations to be performed by a PLD, determining available clock resources of the PLD, determining a flow network model corresponding to the design and the PLD, and determining a clock resource placement based on the flow network model. The flow network model may include a plurality of levels of vertices disposed between source and sink vertices, where vertices are coupled to each other using edges with unit capacity.Type: GrantFiled: April 28, 2015Date of Patent: June 6, 2017Assignee: Lattice Semiconductor CorporationInventors: Chih-Chung Chen, Yanhua Yi
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Publication number: 20160321385Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes determining clock resources in a design identifying operations to be performed by a PLD, determining available clock resources of the PLD, determining a flow network model corresponding to the design and the PLD, and determining a clock resource placement based on the flow network model. The flow network model may include a plurality of levels of vertices disposed between source and sink vertices, where vertices are coupled to each other using edges with unit capacity.Type: ApplicationFiled: April 28, 2015Publication date: November 3, 2016Inventors: Chih-Chung Chen, Yanhua Yi
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Patent number: 9390220Abstract: A place and route technique is provided for a programmable logic device to optimize a delay difference between a bus including a plurality of clock to out paths and a corresponding clock out path.Type: GrantFiled: July 23, 2014Date of Patent: July 12, 2016Assignee: LATTICE SEMICONDUCTOR CORPORATIONInventors: Yanhua Yi, Jun Zhao
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Patent number: 9330217Abstract: Various techniques are provided to correct for hold time violations using input/output (I/O) block hardware of a programmable logic device (PLD) without requiring additional mapping, placement, or routing operations. In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD. The method also includes assigning components of the PLD to perform the operations. The method also includes routing a signal path among the components. The method also includes detecting a hold time violation for the signal path at an I/O block of the PLD. The method also includes selectively adjusting a variable delay cell of the I/O block to correct the hold time violation.Type: GrantFiled: June 24, 2014Date of Patent: May 3, 2016Assignee: LATTICE SEMICONDUCTOR CORPORATIONInventors: Yanhua Yi, Jun Zhao
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Publication number: 20160026745Abstract: A place and route technique is provided for a programmable logic device to optimize a delay difference between a clock to out path and a clock out path.Type: ApplicationFiled: July 23, 2014Publication date: January 28, 2016Inventors: Yanhua Yi, Jun Zhao, Richard Sun
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Publication number: 20160026746Abstract: A place and route technique is provided for a programmable logic device to optimize a delay difference between a bus including a plurality of clock to out paths and a corresponding clock out path.Type: ApplicationFiled: July 23, 2014Publication date: January 28, 2016Inventors: Yanhua Yi, Jun Zhao
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Publication number: 20150370941Abstract: Various techniques are provided to correct for hold time violations using input/output (I/O) block hardware of a programmable logic device (PLD) without requiring additional mapping, placement, or routing operations. In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD. The method also includes assigning components of the PLD to perform the operations. The method also includes routing a signal path among the components. The method also includes detecting a hold time violation for the signal path at an I/O block of the PLD. The method also includes selectively adjusting a variable delay cell of the I/O block to correct the hold time violation.Type: ApplicationFiled: June 24, 2014Publication date: December 24, 2015Inventors: Yanhua Yi, Jun Zhao
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Patent number: 8181139Abstract: In one embodiment of the invention, a computer-implemented method of configuring a programmable logic device (PLD) includes placing logical functions within logical resources of the PLD to implement a desired netlist; swapping the logical function of at least one logical resource with the logical function of at least one other logical resource within the PLD; and evaluating whether to accept or reject the swap using a simulated annealing process that calculates at least three cost function values based upon routing priority groups, timing priority groups, and a timing critical group.Type: GrantFiled: December 22, 2008Date of Patent: May 15, 2012Assignee: Lattice Semicondutor CorporationInventors: Xiaotao Chen, Eric Ting, Ruofan Xu, Yanhua Yi, Jun Zhao
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Patent number: 7757198Abstract: Systems and methods provide techniques to support design specific testing for programmable logic devices in accordance with one or more embodiments. For example in one embodiment, a method of generating configuration data for a programmable logic device includes mapping a design for the programmable logic device, wherein the mapped design incorporates scan test logic; placing and routing the mapped design; and generating configuration data based on the mapped design, wherein the incorporated scan test logic is disabled and not selectable within the programmable logic device configured with the configuration data. The method may further include generating a second configuration data based on the mapped design, wherein the incorporated scan test logic is enabled and selectable within the programmable logic device configured with the second configuration data.Type: GrantFiled: October 19, 2007Date of Patent: July 13, 2010Assignee: Lattice Semiconductor CorporationInventors: Jun Zhao, Yanhua Yi, Eric Ting