Patents by Inventor Yanwei Wang
Yanwei Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11993541Abstract: The present invention discloses a multitype-adsorptive-group polycarboxylic acid water-reducing agent, consisting of 30-60 wt % of a macromolecule with multitype-adsorptive groups and water, the macromolecule with multitype-adsorptive groups has a polyethylene glycol side chain, and adsorption groups of the polymer backbone include a carboxylic acid group, a sulfonic acid group and a phosphoric acid group, the phosphoric acid group being linked to the backbone of the macromolecule with multitype-adsorptive groups by nucleophilic addition. The water-reducing agent of the present invention has significantly improved adaptability to different cements and aggregates while maintaining a high water reduction efficiency, compared with the conventional polycarboxylic acid water-reducing agent agent. It has a good water reducing efficiency in many different grades of cement, as well as a better resistance to aggregates containing more impurities such as machine-made sand.Type: GrantFiled: April 18, 2019Date of Patent: May 28, 2024Assignees: SOBUTE NEW MATERIALS CO., LTD., NANJING BOTE NEW MATERIALS CO., LTD.Inventors: Jiaping Liu, Han Yan, Yong Yang, Jinzhi Liu, Xin Shu, Xiumei Wang, Yanwei Wang, Cheng Yu, Qianping Ran
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Patent number: 11984079Abstract: Provided is a display panel. The display panel includes: a substrate, at least one row of light-emitting elements disposed on the substrate, a plurality of pixel drive circuits, a plurality of connection lines, and a plurality of compensation portions. A length of a first connection line electrically connected to a first pixel drive circuit is less than a length of a second connection line electrically connected to a second pixel drive circuit. A capacitance of the first connection line is compensated by electrically connecting the compensation portion to the first connection line, and thus a difference between the capacitance of the first connection line and a capacitance of the second connection line is reduced.Type: GrantFiled: May 12, 2022Date of Patent: May 14, 2024Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Yanwei Lu, Bangqing Xiao, Jianchang Cai, Benlian Wang, Yao Huang, Yue Long
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Patent number: 11961423Abstract: An electronic shelf label positioning system, an electronic shelf label and a guide rail. The electronic shelf label positioning system includes the electronic shelf label, the guide rail, a PDA and a background server. The electronic shelf label includes a main control SoC, a card reader IC, a screen and a power supply device. The main control SoC is configured to control the screen display and to communicate with an AP. The power supply device is configured to supply power to the electronic shelf label. The guide rail includes a guide rail identification area and a label area. The label area is installed with a plurality of wireless labels each having a unique non-repeated ID number. The guide rail identification area is installed with an identity recognition device, which includes a guide rail ID consisting of the ID numbers of the wireless labels sequentially arranged and summarized.Type: GrantFiled: May 9, 2023Date of Patent: April 16, 2024Assignee: HANSHOW TECHNOLOGY CO., LTD.Inventors: Shiguo Hou, Jianguo Zhao, Min Liang, Le Zhuo, Sheng Yi, Yang Zhao, Yanwei Wang, Linjiang Wang
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Patent number: 11960430Abstract: A remote mapping method, apparatus and device for computing resources, and a storage medium, which are applied to a server. Said method comprises: identifying each FPGA heterogeneous accelerator card in an FPGA BOX; establishing a network communication connection with each FPGA heterogeneous accelerator card via a network interface of each FPGA heterogeneous accelerator card in the FPGA BOX, and establishing a network communication connection between FPGA heterogeneous accelerator cards; mapping each FPGA heterogeneous accelerator card to the server; establishing network transmission for the established network communication connections, and migrating a control flow and a data flow that are performed by the PCIE to the network transmission; and deploying a target application in the FPGA BOX through the established network transmission, and when running the target application, performing data exchange with the FPGA BOX via the network transmission.Type: GrantFiled: April 26, 2021Date of Patent: April 16, 2024Assignee: INSPUR (BEIJING) ELECTRONIC INFORMATION INDUSTRY CO., LTD.Inventors: Yanwei Wang, Rengang Li, Hongwei Kan
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Patent number: 11920688Abstract: A modular valve system includes a modular valve body having an inlet, an outlet, a through-hole, and a fluid flow path between the inlet and the outlet. The modular valve body is used to assemble any one of a pressure regulating valve, a slam-shut valve, or a flow control valve, and the through-hole is configured to receive a component of any one of the pressure regulating valve, the slam-shut valve, and the flow control valve.Type: GrantFiled: September 16, 2020Date of Patent: March 5, 2024Assignee: FISHER JEON GAS EQUIPMENT (CHENGDU) CO., LTD.Inventors: Jie Yuan, Guolei Fan, Yanwei Lei, Le Wang
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Publication number: 20240072340Abstract: A battery housing includes a plate body. The plate body has multiple folding portions and multiple side plates connected by the folding portions. The plate body is folded along the folding portions such that the side plates are connected to create an accommodating space for accommodating an electrochemical unit inside the middle housing.Type: ApplicationFiled: November 3, 2023Publication date: February 29, 2024Inventors: Yanping LUAN, Liangliang GU, Bing WANG, Yanwei WEI
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Publication number: 20240071302Abstract: Provided is a display panel. The display panel includes: a substrate, at least one row of light-emitting elements disposed on the substrate, a plurality of pixel drive circuits, a plurality of connection lines, and a plurality of compensation portions. A length of a first connection line electrically connected to a first pixel drive circuit is less than a length of a second connection line electrically connected to a second pixel drive circuit. A capacitance of the first connection line is compensated by electrically connecting the compensation portion to the first connection line, and thus a difference between the capacitance of the first connection line and a capacitance of the second connection line is reduced.Type: ApplicationFiled: May 12, 2022Publication date: February 29, 2024Applicants: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.Inventors: Yanwei LU, Bangqing XIAO, Jianchang CAI, Benlian WANG, Yao HUANG, Yue LONG
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Publication number: 20240045824Abstract: A remote mapping method, apparatus and device for computing resources, and a storage medium, which are applied to a server. Said method comprises: identifying each FPGA heterogeneous accelerator card in an FPGA BOX; establishing a network communication connection with each FPGA heterogeneous accelerator card via a network interface of each FPGA heterogeneous accelerator card in the FPGA BOX, and establishing a network communication connection between FPGA heterogeneous accelerator cards; mapping each FPGA heterogeneous accelerator card to the server; establishing network transmission for the established network communication connections, and migrating a control flow and a data flow that are performed by the PCIE to the network transmission; and deploying a target application in the FPGA BOX through the established network transmission, and when running the target application, performing data exchange with the FPGA BOX via the network transmission.Type: ApplicationFiled: April 26, 2021Publication date: February 8, 2024Inventors: Yanwei WANG, Rengang LI, Hongwei KAN
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Publication number: 20240048172Abstract: The present disclosure provides a signal communication terminal and a signal communication system. The signal communication terminal includes at least a set of signal enhancement branches and a routing circuit connected with each of the signal enhancement branches. The signal enhancement branch includes a first antenna, a second antenna, a first switching circuit, a second switching circuit, and a first signal processing circuit, where the first switching circuit is connected with each of the first antenna and the first signal processing circuit, the second switching circuit is connected with each of the first signal processing circuit and the routing circuit, and the first signal processing circuit is connected with the second antenna, so as to solve the existing technical problem that the speed of the broadband network of the device for converting the mobile network to the broadband network will be greatly decreased when the mobile signal is weak.Type: ApplicationFiled: September 14, 2022Publication date: February 8, 2024Inventors: Songlin ZHOU, Yanlin Xie, Yanwei Wang
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Patent number: 11833710Abstract: A method for producing an ultra-stable and enhanced solid wood flooring for under-floor heating via surface compression technique includes: subjecting, while subjecting a solid wood to surface compression and enhancement, the solid wood to primary stabilization treatment by controlling a temperature of a hot pressing plate to obtain a compressed enhanced solid wood; putting the compressed enhanced solid wood into a heat treatment tank; and subjecting the compressed enhanced solid wood to secondary stabilization treatment by controlling a pressure and a temperature of steam or air in the heat treatment tank and a treatment time to obtain a finished product. The ultra-stable surface-compressed enhanced solid wood flooring produced by the method features high dimensional stability, low set-recovery after water absorption, and desired moisture and heat resistance.Type: GrantFiled: July 9, 2021Date of Patent: December 5, 2023Assignee: JIUSHENG WOOD CO., LTDInventors: Rongfeng Huang, Yanwei Wang, Enjiu Zhang, Kai Zhang, Xinmin Qian, Fanxu Kong, Xiaoyu He, Hailong Shao, Longxiang Sun
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Publication number: 20230360317Abstract: A digital image processing method performed by a computer is disclosed. A digital image captured by a real camera having intrinsic and extrinsic parameters is received. The intrinsic parameters include a native principal point defined relative to an origin of a coordinate system of the digital image. The digital image is sub-divided into a plurality of sub-images. For each sub-image of the plurality of sub-images, the sub-image is associated with a synthesized recapture camera having synthesized intrinsic and extrinsic parameters mapped from the real camera. The synthesized intrinsic parameters include the native principal point defined relative to an origin of a coordinate system of the sub-image.Type: ApplicationFiled: May 4, 2022Publication date: November 9, 2023Applicant: Microsoft Technology Licensing, LLCInventors: Yanwei WANG, Pascal PARE, Christopher Douglas EDMONDS, Mark Anthony PLAGGE
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Publication number: 20230280397Abstract: The present disclosure discloses an oscillation handling method, an apparatus using the same, and a storage medium. The method includes: obtaining one of a real-time detection voltage and a real-time power of an oscillation system; reducing a gain of the system according to a preset first attenuation value; determining whether the real-time detection voltage meets a first oscillation determination condition; if yes, increase an oscillation determination number by one; restoring the gain of the system to obtain the second real-time detection voltage; determining whether the second real-time detection voltage meets a second oscillation determination condition; if yes, increase the oscillation determination number by two and reduce the gain of the system according to the preset first attenuation value; and determining the preset first attenuation value as a determined oscillation attenuation value in response to the oscillation determination number being larger than or equal to a preset threshold.Type: ApplicationFiled: April 29, 2022Publication date: September 7, 2023Inventors: Chuanzhen OU, Yanlin Xie, Yanwei Wang
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Publication number: 20230274667Abstract: An electronic shelf label positioning system, an electronic shelf label and a guide rail. The electronic shelf label positioning system includes the electronic shelf label, the guide rail, a PDA and a background server. The electronic shelf label includes a main control SoC, a card reader IC, a screen and a power supply device. The main control SoC is configured to control the screen display and to communicate with an AP. The power supply device is configured to supply power to the electronic shelf label. The guide rail includes a guide rail identification area and a label area. The label area is installed with a plurality of wireless labels each having a unique non-repeated ID number. The guide rail identification area is installed with an identity recognition device, which includes a guide rail ID consisting of the ID numbers of the wireless labels sequentially arranged and summarized.Type: ApplicationFiled: May 9, 2023Publication date: August 31, 2023Inventors: Shiguo HOU, Jianguo ZHAO, Min LIANG, Le ZHUO, Sheng YI, Yang ZHAO, Yanwei WANG, Linjiang WANG
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Publication number: 20230214286Abstract: An information recording method, apparatus, and device, and a readable storage medium are provided. The method includes: when a server is started, determining a ring buffer in a Double Data Rate (DDR) of a Field-Programmable Gate Array (FPGA) acceleration card based on an OpenPower platform; determining a start address and an end address of the ring buffer and configuring the start address and the end address to the FPGA acceleration card; and during a running process of the server, recording preset debugging information to the ring buffer in real time, so as to perform fault location according to data in the ring buffer after a fault occurs in the server. According to the present application, during a running process of a server, preset debugging information is recorded using a DDR of an FPGA acceleration card; therefore, when a down fault causes a Central Processing Unit (CPU) error of a server, recording of debugging information can also be ensured, thereby facilitating fault location.Type: ApplicationFiled: February 19, 2021Publication date: July 6, 2023Inventors: Zhenhui LI, Rui HAO, Yanwei WANG
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Patent number: 11687242Abstract: The method includes: an FPGA board feeds back the quantity of controllers and the total quantity of DDR memories after receiving a hardware information acquisition request from a host; after a data space application request is received from the host, on the basis of the data space application request, perform data slice processing on data to be calculated, wherein the data space application request carries the dedicated application space capacity of each DDR and the data to be calculated, and the total quantity of slices of the data to be calculated is the same as the total quantity of DDR memories; and transmit each sliced data to a corresponding DDR space, and according to a data storage position of the sliced data in each DDR, read the data from the DDR memory space in parallel by means of the plurality of controllers and calculate same.Type: GrantFiled: February 19, 2021Date of Patent: June 27, 2023Assignee: INSPUR ELECTRONIC INFORMATION INDUSTRY CO., LTD.Inventors: Jiaheng Fan, Yanwei Wang, Hongwei Kan, Rui Hao
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Publication number: 20230195310Abstract: The method includes: an FPGA board feeds back the quantity of controllers and the total quantity of DDR memories after receiving a hardware information acquisition request from a host; after a data space application request is received from the host, on the basis of the data space application request, perform data slice processing on data to be calculated, wherein the data space application request carries the dedicated application space capacity of each DDR and the data to be calculated, and the total quantity of slices of the data to be calculated is the same as the total quantity of DDR memories; and transmit each sliced data to a corresponding DDR space, and according to a data storage position of the sliced data in each DDR, read the data from the DDR memory space in parallel by means of the plurality of controllers and calculate same.Type: ApplicationFiled: February 19, 2021Publication date: June 22, 2023Inventors: Jiaheng FAN, Yanwei WANG, Hongwei KAN, Rui HAO
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Publication number: 20230127773Abstract: A method for producing an ultra-stable and enhanced solid wood flooring for under-floor heating via surface compression technique includes: subjecting, while subjecting a solid wood to surface compression and enhancement, the solid wood to primary stabilization treatment by controlling a temperature of a hot pressing plate to obtain a compressed enhanced solid wood; putting the compressed enhanced solid wood into a heat treatment tank; and subjecting the compressed enhanced solid wood to secondary stabilization treatment by controlling a pressure and a temperature of steam or air in the heat treatment tank and a treatment time to obtain a finished product. The ultra-stable surface-compressed enhanced solid wood flooring produced by the method features high dimensional stability, low set-recovery after water absorption, and desired moisture and heat resistance.Type: ApplicationFiled: July 9, 2021Publication date: April 27, 2023Applicant: JIUSHENG WOOD CO., LTDInventors: Rongfeng HUANG, Yanwei WANG, Enjiu ZHANG, Kai ZHANG, Xinmin QIAN, Fanxu KONG, Xiaoyu HE, Hailong SHAO, Longxiang SUN
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Patent number: D988301Type: GrantFiled: August 13, 2021Date of Patent: June 6, 2023Assignee: SHENZHEN HUAPTEC CO., LTD.Inventors: Yanwei Wang, Zhiping Chen
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Patent number: D988302Type: GrantFiled: August 13, 2021Date of Patent: June 6, 2023Assignee: SHENZHEN HUAPTEC CO., LTD.Inventors: Yanwei Wang, Zhiping Chen
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Patent number: D990470Type: GrantFiled: August 13, 2021Date of Patent: June 27, 2023Assignee: SHENZHEN HUAPTEC CO., LTD.Inventors: Yanwei Wang, Zhiping Chen