Abstract: The present disclosure provides a solid-state drive with detachable capacitor housing portion. The solid-state drive comprises a first housing portion, a second housing portion and a capacitor housing portion, wherein the first housing portion and the second housing portion are detachably connected and the capacitor housing is detachably connected to at least one of the first housing portion or the second housing portion. A metal dome is embedded in the capacitor housing portion, the solid-state drive is provided with a printed circuit board. When the metal dome is connected to the connecting point(s) on the printed circuit board, an electrical signal is generated to indicate whether the capacitor housing portion and the printed circuit board are correctly installed.

Abstract: The present disclosure provides a packaging-level chip and a chip module packaged with a magnetic cover, and an electronic product. The packaging-level chip packaged with a magnetic cover comprises a die, a packaging material, a substrate and a magnetic cover. The packaging material is packaged on the outside of the die which is arranged on the substrate, and the magnetic cover is packaged on the top of the packaging material and is magnetic.

Abstract: The present disclosure discloses a multilayer circuit board comprising a plurality of metal layers, a blind via and/or a buried via, the multilayer circuit board is capable of transmitting signal between the different metal layers. The blind via has a pad on a non-opening side of the blind via. An upper or lower layer metal layer on the non-opening side of the blind via adjacent to the blind via has a first hole which is located in a position corresponding to the pad on the non-opening side of the blind via in a depth direction of the blind via; and/or an upper and/or lower layer adjacent to the buried via has a second hole which is located in a position corresponding to the pad of an upper and/or lower orifice of the buried via in a depth direction of the buried via.

Abstract: The present disclosure provides a packaging-level chip and a chip module packaged with a magnetic cover, and an electronic product. The packaging-level chip packaged with a magnetic cover comprises a die, a packaging material, a substrate and a magnetic cover. The packaging material is packaged on the outside of the die which is arranged on the substrate, and the magnetic cover is packaged on the top of the packaging material and is magnetic.

Abstract: The present disclosure discloses a multilayer circuit board comprising a plurality of metal layers, a blind via and/or a buried via, the multilayer circuit board is capable of transmitting signal between the different metal layers. The blind via has a pad on a non-opening side of the blind via. An upper or lower layer metal layer on the non-opening side of the blind via adjacent to the blind via has a first hole which is located in a position corresponding to the pad on the non-opening side of the blind via in a depth direction of the blind via; and/or an upper and/or lower layer adjacent to the buried via has a second hole which is located in a position corresponding to the pad of an upper and/or lower orifice of the buried via in a depth direction of the buried via.

Abstract: Systems and apparatus are provided for a removable non-volatile storage device. An exemplary embodiment may provide an apparatus that may comprise a package that may have a first and a second sets of contact pins. The package may have a dimension and the first set of contact pins may be arranged according to a specification of a first type of storage device. The second set of contact pins may be configured to conduct a subset of electrical signals for a second type of storage device. The package may further comprise a controller inside the package and configured to function as the first type of storage device when the first set of contact pins are electrically connected to a host and as the second type of storage device when both the first set and the second set of contact pins are electrically connected to the host.

Abstract: Apparatus and methods are provided for providing thermal management for semiconductor packages or PCBs. In an exemplary embodiment, there is provided a circuit assembly that may comprise a plurality of metal layers each having exposed edges along peripheral sides of a respective metal layer and a thermal coating layer covering an outer surface of the circuit assembly. The thermal coating layer may be in direct contact with the exposed edges of each of the plurality of metal layers at the peripheral sides of the respective metal layer.

Abstract: Apparatus and methods are provided for providing provide high-speed traces in inner layers of semiconductor packages or PCBs. In an exemplary embodiment, there is provided an circuit assembly that may comprise a first ground reference plane, a second ground reference plane and a dielectric layer between the first ground reference plane and the second ground reference plane. The dielectric layer may comprise a pair of traces embedded therein and the first ground reference plane may have an opening corresponding to the pair of traces. The opening may have a width equal to or larger than a width of the pair of traces, which may be equal to widths of respective traces of the pair of traces and a gap between the pair of traces.

Abstract: A semiconductor device including control switches enabling a semiconductor die in a stack of semiconductor die to send or receive a signal, while electrically isolating the remaining die in the die stack. Parasitic pin cap is reduced or avoided by electrically isolating the non-enabled semiconductor die in the die stack.

Abstract: A semiconductor device including control switches enabling a semiconductor die in a stack of semiconductor die to send or receive a signal, while electrically isolating the remaining die in the die stack. Parasitic pin cap is reduced or avoided by electrically isolating the non-enabled semiconductor die in the die stack.