Patents by Inventor Yanzhe Liu
Yanzhe Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240061617Abstract: Systems, apparatuses, and methods for addressing bank hotspotting are described. A computing system includes a memory controller with an arbiter for determining how to arbitrate access to one or more memory device(s) for received requests. The arbiter categorizes each request in a manner that helps to ensure fair virtual channel distribution across the banks of the memory device(s). The category system includes bank hotspotting functions to give banks that have more requests more chances to go over banks with fewer requests. The category system is implemented proportionally with more category credits given to banks with higher bank depths within the virtual channel.Type: ApplicationFiled: October 30, 2023Publication date: February 22, 2024Applicant: Apple Inc.Inventors: Gregory S. Mathews, Kai Lun Hsiung, Lakshmi Narasimha Murthy Nukala, Shane J. Keil, Thejasvi Magudilu Vijayaraj, Yanzhe Liu, Tao Zhang
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Publication number: 20220357879Abstract: Systems, apparatuses, and methods for addressing bank hotspotting are described. A computing system includes a memory controller with an arbiter for determining how to arbitrate access to one or more memory device(s) for received requests. The arbiter categorizes each request in a manner that helps to ensure fair virtual channel distribution across the banks of the memory device(s). The category system includes bank hotspotting functions to give banks that have more requests more chances to go over banks with fewer requests. The category system is implemented proportionally with more category credits given to banks with higher bank depths within the virtual channel.Type: ApplicationFiled: May 6, 2021Publication date: November 10, 2022Inventors: Gregory S. Mathews, Kai Lun Hsiung, Lakshmi Narasimha Murthy Nukala, Shane J. Keil, Thejasvi Magudilu Vijayaraj, Yanzhe Liu, Tao Zhang
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Patent number: 11403037Abstract: An apparatus includes a memory circuit and a memory controller circuit. The memory controller circuit may include a write request queue. The memory controller circuit may be configured to receive a memory request to access the memory circuit and determine if the memory request includes a read request or a write request. A received read request may be scheduled for execution, while a received write request may be stored in the write request queue. The memory controller circuit may reorder scheduled memory requests based on achieving a specified memory access efficiency and based on a number of write requests stored in the write request queue.Type: GrantFiled: June 8, 2020Date of Patent: August 2, 2022Assignee: Apple Inc.Inventors: Shane J. Keil, Gregory S. Mathews, Lakshmi Narasimha Murthy Nukala, Thejasvi Magudilu Vijayaraj, Kai Lun Hsiung, Yanzhe Liu, Sukalpa Biswas
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Patent number: 11221798Abstract: Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller is configured to transition between read turns and writes turn according to a turn schedule. In some embodiments, the memory controller also receives reports from circuitry requesting memory transactions and determines a current latency tolerance value based on the reports. In some embodiments, the memory controller is configured to switch from a write turn to a read turn prior to a scheduled switch based on the current latency tolerance meeting a threshold value.Type: GrantFiled: January 24, 2020Date of Patent: January 11, 2022Assignee: Apple Inc.Inventors: Gregory S. Mathews, Kai Lun Hsiung, Lakshmi Narasimha Murthy Nukala, Peter Fu, Rakesh L. Notani, Sukalpa Biswas, Thejasvi Magudilu Vijayaraj, Yanzhe Liu, Shane J. Keil
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Patent number: 10872652Abstract: A method and apparatus for optimizing calibrations of a memory subsystem is disclosed. A memory controller of a memory subsystem includes a memory interface suitable for coupling to a DRAM having a plurality of banks. The memory controller includes a state machine the state machine may initiate calibration of circuitry within the memory controller. Responsive to initiating the calibration, the state machine also causes a refresh command to be transmitted to the DRAM. The calibration is then performed concurrent with the refresh of the DRAM. Subsequent to transmitting the refresh command, the state machine causes the memory interface to be placed into a low power state.Type: GrantFiled: June 19, 2018Date of Patent: December 22, 2020Assignee: Apple Inc.Inventors: Rakesh L. Notani, Lakshmi Narasimha Murthy Nukala, Kai Lun Hsiung, Sukalpa Biswas, Yanzhe Liu
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Publication number: 20200301615Abstract: An apparatus includes a memory circuit and a memory controller circuit. The memory controller circuit may include a write request queue. The memory controller circuit may be configured to receive a memory request to access the memory circuit and determine if the memory request includes a read request or a write request. A received read request may be scheduled for execution, while a received write request may be stored in the write request queue. The memory controller circuit may reorder scheduled memory requests based on achieving a specified memory access efficiency and based on a number of write requests stored in the write request queue.Type: ApplicationFiled: June 8, 2020Publication date: September 24, 2020Inventors: Shane J. Keil, Gregory S. Mathews, Lakshmi Narasimha Murthy Nukala, Thejasvi Magudilu Vijayaraj, Kai Lun Hsiung, Yanzhe Liu, Sukalpa Biswas
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Publication number: 20200266810Abstract: A method and apparatus for performing duty cycle correction with read/write calibrations is disclosed. A first calibration is performed in a memory subsystem having a memory and a memory controller. The first calibration includes conveying a first clock signal from the memory controller to the memory, and determining the duty cycle of the first clock signal. If the duty cycle is not within a specified range, the duty cycle is adjusted and the process repeated. After the duty cycle of the first clock signal is within the specified range, a second calibration is performed, the second calibration including conveying a second clock signal from the memory to the memory controller. The duty cycle of the first clock signal may be further adjusted based on the second calibration.Type: ApplicationFiled: February 15, 2019Publication date: August 20, 2020Inventors: Robert E. Jeter, Rakesh L. Notani, Kai Lun Hsiung, Yanzhe Liu
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Patent number: 10734983Abstract: A method and apparatus for performing duty cycle correction with read/write calibrations is disclosed. A first calibration is performed in a memory subsystem having a memory and a memory controller. The first calibration includes conveying a first clock signal from the memory controller to the memory, and determining the duty cycle of the first clock signal. If the duty cycle is not within a specified range, the duty cycle is adjusted and the process repeated. After the duty cycle of the first clock signal is within the specified range, a second calibration is performed, the second calibration including conveying a second clock signal from the memory to the memory controller. The duty cycle of the first clock signal may be further adjusted based on the second calibration.Type: GrantFiled: February 15, 2019Date of Patent: August 4, 2020Assignee: Apple Inc.Inventors: Robert E. Jeter, Rakesh L. Notani, Kai Lun Hsiung, Yanzhe Liu
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Patent number: 10678478Abstract: An embodiment of an apparatus includes a memory circuit and a memory controller circuit. The memory controller circuit may include a write request queue. The memory controller circuit may be configured to receive a memory request to access the memory circuit and determine if the memory request includes a read request or a write request. A received read request may be scheduled for execution, while a received write request may be stored in the write request queue. The memory controller circuit may reorder scheduled memory requests based on achieving a specified memory access efficiency and based on a number of write requests stored in the write request queue.Type: GrantFiled: August 24, 2018Date of Patent: June 9, 2020Assignee: Apple Inc.Inventors: Shane J. Keil, Gregory S. Mathews, Lakshmi Narasimha Murthy Nukala, Thejasvi Magudilu Vijayaraj, Kai Lun Hsiung, Yanzhe Liu, Sukalpa Biswas
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Publication number: 20200159463Abstract: Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller is configured to transition between read turns and writes turn according to a turn schedule. In some embodiments, the memory controller also receives reports from circuitry requesting memory transactions and determines a current latency tolerance value based on the reports. In some embodiments, the memory controller is configured to switch from a write turn to a read turn prior to a scheduled switch based on the current latency tolerance meeting a threshold value.Type: ApplicationFiled: January 24, 2020Publication date: May 21, 2020Inventors: Gregory S. Mathews, Kai Lun Hsiung, Lakshmi Narasimha Murthy Nukala, Peter Fu, Rakesh L. Notani, Sukalpa Biswas, Thejasvi Magudilu Vijayaraj, Yanzhe Liu, Shane J. Keil
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Publication number: 20200065028Abstract: An embodiment of an apparatus includes a memory circuit and a memory controller circuit. The memory controller circuit may include a write request queue. The memory controller circuit may be configured to receive a memory request to access the memory circuit and determine if the memory request includes a read request or a write request. A received read request may be scheduled for execution, while a received write request may be stored in the write request queue. The memory controller circuit may reorder scheduled memory requests based on achieving a specified memory access efficiency and based on a number of write requests stored in the write request queue.Type: ApplicationFiled: August 24, 2018Publication date: February 27, 2020Inventors: Shane J. Keil, Gregory S. Mathews, Lakshmi Narasimha Murthy Nukala, Thejasvi Magudilu Vijayaraj, Kai Lun Hsiung, Yanzhe Liu, Sukalpa Biswas
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Publication number: 20200057579Abstract: Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller implements a per-bank priority-based arbitration scheme for different types of memory traffic (e.g., with different quality of service parameters). In some embodiments, the memory controller is configured to provide per-bank overrides to the arbitration scheme based on latency tolerance reported by one or more requesters sending a particular type of memory traffic. Various techniques disclosed herein may improve performance, improve fairness among different types of memory traffic, and/or reduce power consumption.Type: ApplicationFiled: August 17, 2018Publication date: February 20, 2020Inventors: Gregory S. Mathews, Kai Lun Hsiung, Lakshmi Narasimha Murthy Nukala, Peter Fu, Rakesh L. Notani, Sukalpa Biswas, Thejasvi Magudilu Vijayaraj, Yanzhe Liu, Shane J. Keil
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Patent number: 10545701Abstract: Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller implements a per-bank priority-based arbitration scheme for different types of memory traffic (e.g., with different quality of service parameters). In some embodiments, the memory controller is configured to provide per-bank overrides to the arbitration scheme based on latency tolerance reported by one or more requesters sending a particular type of memory traffic. Various techniques disclosed herein may improve performance, improve fairness among different types of memory traffic, and/or reduce power consumption.Type: GrantFiled: August 17, 2018Date of Patent: January 28, 2020Assignee: Apple Inc.Inventors: Gregory S. Mathews, Kai Lun Hsiung, Lakshmi Narasimha Murthy Nukala, Peter Fu, Rakesh L. Notani, Sukalpa Biswas, Thejasvi Magudilu Vijayaraj, Yanzhe Liu, Shane J. Keil
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Publication number: 20190385670Abstract: A method and apparatus for optimizing calibrations of a memory subsystem is disclosed. A memory controller of a memory subsystem includes a memory interface suitable for coupling to a DRAM having a plurality of banks. The memory controller includes a state machine the state machine may initiate calibration of circuitry within the memory controller. Responsive to initiating the calibration, the state machine also causes a refresh command to be transmitted to the DRAM. The calibration is then performed concurrent with the refresh of the DRAM. Subsequent to transmitting the refresh command, the state machine causes the memory interface to be placed into a low power state.Type: ApplicationFiled: June 19, 2018Publication date: December 19, 2019Inventors: Rakesh L. Notani, Lakshmi Narasimha Murthy Nukala, Kai Lun Hsiung, Sukalpa Biswas, Yanzhe Liu
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Patent number: 9478263Abstract: Systems and methods for monitoring and controlling repetitive accesses to a dynamic random-access memory (DRAM) row are disclosed. A method for monitoring and controlling repetitive accesses to a DRAM can include dividing a bank of the DRAM into a number of logical blocks, mapping each row of the bank to one of the logical blocks, monitoring accesses to the logical blocks, and controlling accesses to the logical blocks based on the monitoring.Type: GrantFiled: January 17, 2014Date of Patent: October 25, 2016Assignee: APPLE INC.Inventors: Bin Ni, Kai Lun Charles Hsiung, Yanzhe Liu, Sukalpa Biswas
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Patent number: 9384820Abstract: A method and apparatus for aligning calibration segments for increased availability of a memory subsystem is disclosed. In one embodiment, a memory subsystem includes a memory and a memory controller coupled thereto via a number of independently operable channels (interfaces). The memory controller may convey on each of the channels at least one corresponding data strobe signal. The data strobe signal in each channel may be periodically calibrated. The memory controller may be configured to align the periodic calibrations in time so that they are performed concurrently instead of in a staggered manner. During the time the calibrations are performed on each channel, the memory may be unavailable for normal accesses.Type: GrantFiled: June 12, 2015Date of Patent: July 5, 2016Assignee: Apple Inc.Inventors: Neeraj Parik, Thejasvi Magudilu Vijayaraj, Kai Lun Hsiung, Yanzhe Liu
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Publication number: 20150206558Abstract: Systems and methods for monitoring and controlling repetitive accesses to a dynamic random-access memory (DRAM) row are disclosed. A method for monitoring and controlling repetitive accesses to a DRAM can include dividing a bank of the DRAM into a number of logical blocks, mapping each row of the bank to one of the logical blocks, monitoring accesses to the logical blocks, and controlling accesses to the logical blocks based on the monitoring.Type: ApplicationFiled: January 17, 2014Publication date: July 23, 2015Applicant: Apple Inc.Inventors: Bin Ni, Kai Lun Charles Hsiung, Yanzhe Liu, Sukalpa Biswas