Abstract: A memory includes a substrate, a control circuit layer located in the substrate, and at least two memory structure layers. The control circuit layer includes at least part of control circuits of the memory. The at least two memory structure layers are sequentially stacked on the control circuit layer. Each memory structure layer includes multiple memory blocks arranged in an array. The memory block includes multiple parallel Word Lines (WLs) extending in a first direction. The first direction is parallel to a surface of the substrate. An opening is provided between adjacent memory blocks located in the same memory structure layer. The openings located in different memory structure layers go through each other. WLs in the at least one memory structure layer are connected to the control circuit layer through the openings that go through each other.

Abstract: Provided is a semiconductor structure and a method for manufacturing the same, a memory and a method for operating the same. The semiconductor includes a substrate having a plurality of active areas close to a surface of the substrate; a gate structure located in a first structure layer on the substrate, in which the gate structure and the active areas constitute a selective transistor; and an anti-fuse bit structure located in a second structure layer on the first structure layer, and connected with an active area of one selective transistor through a first connecting structure, in which a breakdown state and a non-breakdown state of the anti-fuse bit structure represent different stored data.

Abstract: Disclosed are a semiconductor structure, a memory and a method for operating the memory. The semiconductor structure includes: a substrate; a first gate structure and a second gate structure that are located on a surface of the substrate and have a same thickness smaller than a preset thickness; and a first doped area and a second doped area that are located in the substrate and are respectively located on two sides of the first gate structure. The first gate structure forms a selection transistor with the first and second doped areas; an orthographic projection of the second gate structure on the substrate is at least partially overlapped with the second doped area. The second gate structure and the second doped area form an antifuse bit structure. A breakdown state and a non-breakdown state of the antifuse bit structure are configured to represent different stored data.

Abstract: A resistive memory apparatus and a method of operating a resistive memory apparatus are disclosed. In an embodiment, a resistive memory apparatus can include a memory cell that includes at least two transistors and a resistive element. The resistive memory apparatus can further include a bit line through which data is exchanged with the memory cell, wherein the bit line electronically interconnects with the memory cell, and a bit line regulator connected to the bit line. The bit line regulator can regulate the bit line based on the state of the resistive element. The forming signals and voltage settings can be transmitted over the bit line regulator and across the bit line to the memory cell.

Abstract: A resistive memory apparatus and a method of operating a resistive memory apparatus are disclosed. In an embodiment, a resistive memory apparatus can include a memory cell that includes at least two transistors and a resistive element. The resistive memory apparatus can further include a bit line through which data is exchanged with the memory cell, wherein the bit line electronically interconnects with the memory cell, and a bit line regulator connected to the bit line. The bit line regulator can regulate the bit line based on the state of the resistive element. The forming signals and voltage settings can be transmitted over the bit line regulator and across the bit line to the memory cell.

Abstract: A device and method of forming the device using a split gate embedded memory technology are presented. The device includes two polysilicon layers, one for floating gate poly and the other for logic, HV and stack gate and split gate. An oxide-nitride-oxide process of the manufacturing method results in low reliability risk and good uniformity in the device. Moreover, embodiments of the manufacturing method have good controllability of the profile and critical dimension of select gates in production. Furthermore, there is no need to provide non-volatile memory and high-voltage protection for devices manufactured by embodiments of the manufacturing method of the present disclosure.

Abstract: A device having a substrate prepared with a memory cell region having a memory cell is disclosed. The memory cell includes an access transistor and a storage transistor. The access transistor includes first and second source/drain (S/D) regions and the storage transistor includes first and second storage S/D regions. The access and storage transistors are coupled in series and the second S/D regions being a common S/D region. An erase gate is disposed over the common S/D region. A program gate is disposed over the first storage S/D region. Such an arrangement of the memory cell decouples a program channel and an erase channel.

Abstract: A device and method of forming the device using a split gate embedded memory technology are presented. The device includes two polysilicon layers, one for floating gate poly and the other for logic, HV and stack gate and split gate. An oxide-nitride-oxide process of the manufacturing method results in low reliability risk and good uniformity in the device. Moreover, embodiments of the manufacturing method have good controllability of the profile and critical dimension of select gates in production. Furthermore, there is no need to provide non-volatile memory and high-voltage protection for devices manufactured by embodiments of the manufacturing method of the present disclosure.

Abstract: A device having a substrate prepared with a memory cell region having a memory cell is disclosed. The memory cell includes an access transistor and a storage transistor. The access transistor includes first and second source/drain (S/D) regions and the storage transistor includes first and second storage S/D regions. The access and storage transistors are coupled in series and the second S/D regions being a common S/D region. An erase gate is disposed over the common S/D region. A program gate is disposed over the first storage S/D region. Such an arrangement of the memory cell decouples a program channel and an erase channel.

Abstract: A device having a substrate prepared with a memory cell region having a memory cell is disclosed. The memory cell includes an access transistor and a storage transistor. The access transistor includes first and second source/drain (S/D) regions and the storage transistor includes first and second storage S/D regions. The access and storage transistors are coupled in series and the second S/D regions being a common S/D region. An erase gate is disposed over the common S/D region. A program gate is disposed over the first storage S/D region. Such an arrangement of the memory cell decouples a program channel and an erase channel.

Abstract: A device having a substrate prepared with a memory cell region having a memory cell is disclosed. The memory cell includes an access transistor and a storage transistor. The access transistor includes first and second source/drain (S/D) regions and the storage transistor includes first and second storage S/D regions. The access and storage transistors are coupled in series and the second S/D regions being a common S/D region. An erase gate is disposed over the common S/D region. A program gate is disposed over the first storage S/D region. Such an arrangement of the memory cell decouples a program channel and an erase channel.