Abstract: A semiconductor device includes a first field effect transistor (FET) including a first gate dielectric layer and a first gate electrode. The first gate electrode includes a first lower metal layer and a first upper metal layer. The first lower metal layer includes a first underlying metal layer in contact with the first gate dielectric layer and a first bulk metal layer. A bottom of the first upper metal layer is in contact with an upper surface of the first underlying metal layer and an upper surface of the first bulk metal layer.

Abstract: A semiconductor device includes a first field effect transistor (FET) including a first gate dielectric layer and a first gate electrode. The first gate electrode includes a first lower metal layer and a first upper metal layer. The first lower metal layer includes a first underlying metal layer in contact with the first gate dielectric layer and a first bulk metal layer. A bottom of the first upper metal layer is in contact with an upper surface of the first underlying metal layer and an upper surface of the first bulk metal layer.

Abstract: A semiconductor device includes a first field effect transistor (FET) including a first gate dielectric layer and a first gate electrode. The first gate electrode includes a first lower metal layer and a first upper metal layer. The first lower metal layer includes a first underlying metal layer in contact with the first gate dielectric layer and a first bulk metal layer. A bottom of the first upper metal layer is in contact with an upper surface of the first underlying metal layer and an upper surface of the first bulk metal layer.

Abstract: A semiconductor device includes a first field effect transistor (FET) including a first gate dielectric layer and a first gate electrode. The first gate electrode includes a first lower metal layer and a first upper metal layer. The first lower metal layer includes a first underlying metal layer in contact with the first gate dielectric layer and a first bulk metal layer. A bottom of the first upper metal layer is in contact with an upper surface of the first underlying metal layer and an upper surface of the first bulk metal layer.

Abstract: Source and drain formation techniques are disclosed herein for fin-like field effect transistors (FinFETs). An exemplary method for forming epitaxial source/drain features for a FinFET includes epitaxially growing a semiconductor material on a plurality of fins using a silicon-containing precursor and a chlorine-containing precursor. The semiconductor material merges to form an epitaxial feature spanning the plurality of fins, where the plurality of fins has a fin spacing that is less than about 25 nm. A ratio of a flow rate of the silicon-containing precursor to a flow rate of the chlorine-containing precursor is less than about 5. The method further includes etching back the semiconductor material using the chlorine-containing precursor, thereby modifying a profile of the epitaxial feature. The epitaxially growing and the etching back may be performed only once. In some implementations, where the FinFET is an n-type FinFET, the epitaxially growing also uses a phosphorous-containing precursor.

Abstract: A semiconductor device includes a first field effect transistor (FET) including a first gate dielectric layer and a first gate electrode. The first gate electrode includes a first lower metal layer and a first upper metal layer. The first lower metal layer includes a first underlying metal layer in contact with the first gate dielectric layer and a first bulk metal layer. A bottom of the first upper metal layer is in contact with an upper surface of the first underlying metal layer and an upper surface of the first bulk metal layer.

Abstract: A semiconductor device includes a first field effect transistor (FET) including a first gate dielectric layer and a first gate electrode. The first gate electrode includes a first lower metal layer and a first upper metal layer. The first lower metal layer includes a first underlying metal layer in contact with the first gate dielectric layer and a first bulk metal layer. A bottom of the first upper metal layer is in contact with an upper surface of the first underlying metal layer and an upper surface of the first bulk metal layer.

Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A source/drain region is formed. A first insulating layer is formed over the dummy gate structure and the source/drain region. A gate space is formed by removing the dummy gate structure. The gate space is filled with a first metal layer. A gate recess is formed by removing an upper portion of the filled first metal layer. A second metal layer is formed over the first metal layer in the gate recess. A second insulating layer is formed over the second metal layer in the gate recess.

Abstract: Source and drain formation techniques are disclosed herein for fin-like field effect transistors (FinFETs). An exemplary method for forming epitaxial source/drain features for a FinFET includes epitaxially growing a semiconductor material on a plurality of fins using a silicon-containing precursor and a chlorine-containing precursor. The semiconductor material merges to form an epitaxial feature spanning the plurality of fins, where the plurality of fins has a fin spacing that is less than about 25 nm. A ratio of a flow rate of the silicon-containing precursor to a flow rate of the chlorine-containing precursor is less than about 5. The method further includes etching back the semiconductor material using the chlorine-containing precursor, thereby modifying a profile of the epitaxial feature. The epitaxially growing and the etching back may be performed only once. In some implementations, where the FinFET is an n-type FinFET, the epitaxially growing also uses a phosphorous-containing precursor.

Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A source/drain region is formed. A first insulating layer is formed over the dummy gate structure and the source/drain region. A gate space is formed by removing the dummy gate structure. The gate space is filled with a first metal layer. A gate recess is formed by removing an upper portion of the filled first metal layer. A second metal layer is formed over the first metal layer in the gate recess. A second insulating layer is formed over the second metal layer in the gate recess.

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes implanting a first type of dopants in a first region and a second region of a substrate and implanting a second type of dopants in the second region of the substrate. The method includes forming a material layer over the first region and the second region of the substrate and patterning the material layer, the first region of the substrate, and the second region of the substrate to form a first fin structure and a second fin structure The method includes forming a gate structure across the first fin structure and the second fin structure.

Abstract: A fin field effect transistor (FinFET) device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending above the substrate. The FinFET device structure includes an isolation structure, and the fin structure is embedded in the isolation structure. The FinFET device structure also includes a gate structure formed on a middle portion of the fin structure. The gate structure has a top portion and bottom portion, and the bottom portion is wider than the top portion. The FinFET device structure further includes a source/drain (S/D) structure formed adjacent to the gate structure.

Abstract: A fin field effect transistor (FinFET) device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending above the substrate. The FinFET device structure includes an isolation structure, and the fin structure is embedded in the isolation structure. The FinFET device structure also includes a gate structure formed on a middle portion of the fin structure. The gate structure has a top portion and bottom portion, and the bottom portion is wider than the top portion. The FinFET device structure further includes a source/drain (S/D) structure formed adjacent to the gate structure.

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes implanting a first type of dopants in a first region and a second region of a substrate and implanting a second type of dopants in the second region of the substrate. The method includes forming a material layer over the first region and the second region of the substrate and patterning the material layer, the first region of the substrate, and the second region of the substrate to form a first fin structure and a second fin structure The method includes forming a gate structure across the first fin structure and the second fin structure.

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes implanting a first type of dopants in a first region and a second region and implanting a second type of dopants in the second region. In addition, an un-doped silicon layer is formed over the first and second regions, and a first and a second fin structures are formed. The first fin structure includes a first type of anti-punch through structure implanted with the first type of dopants and a first un-doped silicon structure over the first type of anti-punch through structure, and the second fin structure includes a second type of anti-punch through structure implanted with the second type of dopants and a second un-doped silicon structure formed over the second type of anti-punch through structure.