Patents by Inventor Yao-Jen Fan

Yao-Jen Fan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9857677
    Abstract: A semiconductor layout pattern includes a device layout pattern, a plurality of rectangular first dummy patterns having a first size, a plurality of rectangular second dummy patterns having second sizes, and a plurality of bar-like third dummy patterns having varied third sizes. The pattern densities are smartly equalized by positioning the second dummy patterns.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: January 2, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chen-Hua Tsai, Jian-Cheng Chen, Chin-Yueh Tsai, Yao-Jen Fan, Heng-Kun Chen, Hsiang Yang
  • Patent number: 9672309
    Abstract: A method for generating a layout pattern includes following steps. A basic layout pattern including a plurality of first stripe patterns in a first cluster region is provided. Each first stripe pattern extends in a first direction, and the first stripe patterns have equal pitches in a second direction. A plurality of anchor bar patterns are generated. Each anchor bar pattern extends in the first direction, and the anchor bar patterns have equal pitches in the second direction. Edges of at least one of the anchor bar patterns in the second direction are aligned with edges of two adjacent first stripe patterns respectively. At least one of the anchor bar patterns overlaps a first space between two adjacent first stripe patterns. At least one first mandrel pattern is generated at the first space overlapped by the anchor bar pattern, and the first mandrel pattern is outputted to a photomask.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: June 6, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Harn-Jiunn Wang, Teng-Yao Chang, Chin-Lung Lin, Chih-Hsien Tang, Yao-Jen Fan
  • Patent number: 9529254
    Abstract: A layout pattern decomposition method includes following steps. A layout pattern is received. The layout pattern includes a plurality of features, and an edge-to-edge space is respectively defined in between two adjacent features. A sum of a width of the edge-to-edge space and a width of the feature on a left side of the edge-to-edge space and a sum of the width of the edge-to-edge space and a width of the feature on a right side of the edge-to-edge space are respectively calculated. The sums and a predetermined value are respectively compared. When any one of the sums is smaller than the predetermined value, the two features on the two sides of the edge-to-edge space are colored by a first color and alternatively a second color. The features including the first color are assigned to a first pattern and the features including the second color to a second pattern.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: December 27, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Hsien Tang, Yao-Jen Fan, Chin-Lung Lin
  • Publication number: 20160275226
    Abstract: A method for generating a layout pattern includes following steps. A basic layout pattern including a plurality of first stripe patterns in a first cluster region is provided. Each first stripe pattern extends in a first direction, and the first stripe patterns have equal pitches in a second direction. A plurality of anchor bar patterns are generated. Each anchor bar pattern extends in the first direction, and the anchor bar patterns have equal pitches in the second direction. Edges of at least one of the anchor bar patterns in the second direction are aligned with edges of two adjacent first stripe patterns respectively. At least one of the anchor bar patterns overlaps a first space between two adjacent first stripe patterns. At least one first mandrel pattern is generated at the first space overlapped by the anchor bar pattern, and the first mandrel pattern is outputted to a photomask.
    Type: Application
    Filed: April 27, 2015
    Publication date: September 22, 2016
    Inventors: Harn-Jiunn Wang, Teng-Yao Chang, Chin-Lung Lin, Chih-Hsien Tang, Yao-Jen Fan
  • Publication number: 20160126182
    Abstract: A semiconductor layout pattern includes a device layout pattern, a plurality of rectangular first dummy patterns having a first size, a plurality of rectangular second dummy patterns having second sizes, and a plurality of bar-like third dummy patterns having varied third sizes. The pattern densities are smartly equalized by positioning the second dummy patterns.
    Type: Application
    Filed: January 12, 2016
    Publication date: May 5, 2016
    Inventors: Chen-Hua Tsai, Jian-Cheng Chen, Chin-Yueh Tsai, Yao-Jen Fan, Heng-Kun Chen, Hsiang Yang
  • Patent number: 9268896
    Abstract: A method of forming a photomask comprises providing a predetermined fin array having a plurality of fin patterns to a computer readable medium in a computer system. First of all, a plurality of width markers is defined by using the computer system, with each of the width marker parallel to each other and comprising two fin patterns, wherein each of the width markers is spaced from each other by a space. Then, a number of the width markers is checked to be an even. Following this, a plurality of pre-mandrel patterns is defined corresponding to odd numbered ones of the spaces. Then, a plurality of mandrel patterns is defined by sizing up the pre-mandrel patterns. Finally, the mandrel patterns are outputted to form a photomask.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: February 23, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Hsien Tang, Shih-Hung Tsai, Chun-Hsien Huang, Yao-Jen Fan
  • Patent number: 9269649
    Abstract: A method for generating dummy patterns includes providing a layout region having a layout pattern with a first density, inserting a plurality of first dummy patterns with a second density corresponding to the first density in the layout pattern, dividing the layout region into a plurality of sub-regions with a third density, adjusting a size of the first dummy pattern according to a difference between the second density and the third density, and outputting the layout pattern and the first dummy patterns on a photomask.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: February 23, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chen-Hua Tsai, Jian-Cheng Chen, Chin-Yueh Tsai, Yao-Jen Fan, Heng-Kun Chen, Hsiang Yang
  • Publication number: 20160048072
    Abstract: A layout pattern decomposition method includes following steps. A layout pattern is received. The layout pattern includes a plurality of features, and an edge-to-edge space is respectively defined in between two adjacent features. A sum of a width of the edge-to-edge space and a width of the feature on a left side of the edge-to-edge space and a sum of the width of the edge-to-edge space and a width of the feature on a right side of the edge-to-edge space are respectively calculated. The sums and a predetermined value are respectively compared. When any one of the sums is smaller than the predetermined value, the two features on the two sides of the edge-to-edge space are colored by a first color and alternatively a second color. The features including the first color are assigned to a first pattern and the features including the second color to a second pattern.
    Type: Application
    Filed: October 1, 2014
    Publication date: February 18, 2016
    Inventors: Chih-Hsien Tang, Yao-Jen Fan, Chin-Lung Lin
  • Patent number: 9245822
    Abstract: A semiconductor layout pattern includes a device layout pattern, a plurality of rectangular first dummy patterns having a first size, a plurality of rectangular second dummy patterns having varied second sizes, and a plurality of first via dummy patterns smaller than the second dummy patterns and arranged in a spatial range within the second dummy patterns.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: January 26, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chen-Hua Tsai, Jian-Cheng Chen, Chin-Yueh Tsai, Yao-Jen Fan, Heng-Kun Chen, Hsiang Yang
  • Patent number: 9009633
    Abstract: A method of correcting assist features includes the following steps. At first, a first layout pattern is received by a computer system, and the first layout pattern is split into a plurality of first regions. Subsequently, a plurality of assist features are added into the first layout pattern to form a second layout pattern, wherein at least one of the assist features neighboring any one of the edges of the first regions is defined as a selected pattern. Then, the second layout pattern is split into a plurality of second regions. Afterwards, a check step is performed on the second region including the selected pattern, and the second layout pattern is corrected to form a corrected second layout pattern.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: April 14, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Tsung-Yeh Wu, Chin-Lung Lin, Yao-Jen Fan, Wei-Han Chien, Chia-Chun Tsai
  • Publication number: 20140331191
    Abstract: A method of correcting assist features includes the following steps. At first, a first layout pattern is received by a computer system, and the first layout pattern is split into a plurality of first regions. Subsequently, a plurality of assist features are added into the first layout pattern to form a second layout pattern, wherein at least one of the assist features neighboring any one of the edges of the first regions is defined as a selected pattern. Then, the second layout pattern is split into a plurality of second regions. Afterwards, a check step is performed on the second region including the selected pattern, and the second layout pattern is corrected to form a corrected second layout pattern.
    Type: Application
    Filed: May 6, 2013
    Publication date: November 6, 2014
    Applicant: United Microelectronics Corp.
    Inventors: Tsung-Yeh Wu, Chin-Lung Lin, Yao-Jen Fan, Wei-Han Chien, Chia-Chun Tsai
  • Publication number: 20140042636
    Abstract: A method for generating dummy patterns includes providing a layout region having a layout pattern with a first density, inserting a plurality of first dummy patterns with a second density corresponding to the first density in the layout pattern, dividing the layout region into a plurality of sub-regions with a third density, adjusting a size of the first dummy pattern according to a difference between the second density and the third density, and outputting the layout pattern and the first dummy patterns on a photomask.
    Type: Application
    Filed: October 28, 2013
    Publication date: February 13, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chen-Hua Tsai, Jian-Cheng Chen, Chin-Yueh Tsai, Yao-Jen Fan, Heng-Kun Chen, Hsiang Yang
  • Publication number: 20140042640
    Abstract: A semiconductor layout pattern includes a device layout pattern, a plurality of rectangular first dummy patterns having a first size, a plurality of rectangular second dummy patterns having varied second sizes, and a plurality of first via dummy patterns smaller than the second dummy patterns and arranged in a spatial range within the second dummy patterns.
    Type: Application
    Filed: October 28, 2013
    Publication date: February 13, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chen-Hua Tsai, Jian-Cheng Chen, Chin-Yueh Tsai, Yao-Jen Fan, Heng-Kun Chen, Hsiang Yang
  • Patent number: 8597860
    Abstract: A method for generating dummy patterns includes providing a layout region having a layout pattern with a first density, inserting a plurality of first dummy patterns with a second density corresponding to the first density in the layout pattern, dividing the layout region into a plurality of sub-regions with a third density, adjusting a size of the first dummy pattern according to a difference between the second density and the third density, and outputting the layout pattern and the first dummy patterns on a photomask.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: December 3, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chen-Hua Tsai, Jian-Cheng Chen, Chin-Yueh Tsai, Yao-Jen Fan, Heng-Kun Chen, Hsiang Yang
  • Publication number: 20120295187
    Abstract: A method for generating dummy patterns includes providing a layout region having a layout pattern with a first density, inserting a plurality of first dummy patterns with a second density corresponding to the first density in the layout pattern, dividing the layout region into a plurality of sub-regions with a third density, adjusting a size of the first dummy pattern according to a difference between the second density and the third density, and outputting the layout pattern and the first dummy patterns on a photomask.
    Type: Application
    Filed: May 20, 2011
    Publication date: November 22, 2012
    Inventors: Chen-Hua Tsai, Jian-Cheng Chen, Chin-Yueh Tsai, Yao-Jen Fan, Heng-Kun Chen, Hsiang Yang