Patents by Inventor Yao-Sheng Lin
Yao-Sheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11994787Abstract: An information handling system may include a processor, a memory device, a PMU, and a camera formed into a chassis of the information handling system. The camera includes a lens, a shutter to block the capture of an image by the camera, shutter driver hardware to actuate shutter movement between an open state and a closed state, and a shutter position sensor to detect the position of the shutter. The information handling system includes a microcontroller unit operatively coupled to the camera to receive input describing a set state of the shutter received from user toggle input, compare the set state of the shutter to a detected state of the shutter detected by the shutter position sensor and take remedial action to actuate the shutter driver hardware to change the detected state of the shutter when the detected state of the shutter differs from the set state of the shutter.Type: GrantFiled: July 22, 2022Date of Patent: May 28, 2024Assignee: DELL PRODUCTS LPInventors: Geroncio O. Tan, Daniel L. Hamlin, Yao-Hsien Huang, Yung-Sheng Lin
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Patent number: 11983848Abstract: Aspects of the disclosure provide a frame processor for processing frames with aliasing artifacts. For example, the frame processor can include a super-resolution (SR) and anti-aliasing (AA) engine and an attention reference frame generator coupled to the SR and AA engine. The SR and AA engine can be configured to enhance resolution and remove aliasing artifacts of a frame to generate a first high-resolution frame with aliasing artifacts and a second high-resolution frame with aliasing artifacts removed. The attention reference frame generator can be configured to generate an attention reference frame based on the first high-resolution frame and the second high-resolution frame.Type: GrantFiled: January 6, 2023Date of Patent: May 14, 2024Assignee: MEDIATEK INC.Inventors: Cheng-Lung Jen, Pei-Kuei Tsung, Chih-Wei Chen, Yao-Sheng Wang, Shih-Che Chen, Yu-Sheng Lin, Chih-Wen Goo, Shih-Chin Lin, Tsung-Shian Huang, Ying-Chieh Chen
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Patent number: 11980694Abstract: A sterilization apparatus for a portable electronic device including a cabinet and a carrier is provided. The carrier includes a base slidably disposed on the cabinet, multiple first positioning elements and multiple second positioning elements disposed in parallel on the base, multiple sterilization light sources corresponding to the second positioning elements and multiple pressure sensors disposed in parallel in the base. The base is configured to carry at least one portable electronic device. One second positioning element is disposed between any two adjacent first positioning elements, and any first positioning element and any second positioning element adjacent to each other are separated by a positioning space. The pressure sensors are respectively located in the positioning spaces. One sterilization light source is disposed between any two adjacent pressure sensors, and the pressure sensors are configured to sense a pressure from the portable electronic device.Type: GrantFiled: May 13, 2021Date of Patent: May 14, 2024Assignee: COMPAL ELECTRONICS, INC.Inventors: Yi-Hung Chen, Chih-Wen Chiang, Yun-Tung Pai, Yen-Hua Hsiao, Yao-Kuang Su, Yi-Hsuan Lin, Han-Sheng Siao
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Patent number: 11962015Abstract: Provided are an electrolytic copper foil, an electrode and a lithium-ion cell comprising the same. The electrolytic copper foil has a first surface and a second surface opposite the first surface. An absolute difference of the FWHM of the characteristic peaks of (111) planes of the first surface and the second surface analyzed by GIXRD is less than 0.14, the first and the second surfaces each have a nanoindentation hardness of 0.3 GPa to 3.0 GPa, and the yield strength of the electrolytic copper foil is more than 230 MPa. By controlling the absolute difference of the FWHM of the characteristic peaks of (111) plane of these two surfaces, the nanoindentation hardness of these two surfaces and the yield strength, the electrolytic copper foil can have improved tolerance to the repeated charging and discharging and reduced warpage, thereby improving the yield rate and value of the lithium-ion cell.Type: GrantFiled: September 8, 2022Date of Patent: April 16, 2024Assignee: CHANG CHUN PETROCHEMICAL CO., LTD.Inventors: Ting-Mu Chuang, Sung-Shiuan Lin, Yao-Sheng Lai, Jui-Chang Chou
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Publication number: 20240094104Abstract: An embodiment interfacial bonding test structure may include a first substrate having a first planar surface, a second substrate having a second planar surface that is parallel to the first planar surface, a first semiconductor die, and a second semiconductor die, each semiconductor die bonded between the first substrate and the second substrate thereby forming a sandwich structure. The first semiconductor die and the second semiconductor die may be bonded to the first surface with a first adhesive and may be bonded to the second surface with a second adhesive. The first semiconductor die and the second semiconductor die may be displaced from one another by a first separation along a direction parallel to the first planar surface and the second planar surface. The second substrate may include a notch having an area that overlaps with an area of the first separation in a plan view.Type: ApplicationFiled: April 20, 2023Publication date: March 21, 2024Inventors: Yu-Sheng Lin, Jyun-Lin Wu, Yao-Chun Chuang, Chin-Fu Kao
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Publication number: 20240090796Abstract: A foot sensor and analysis device, which includes a pressure sensing layer arranged inside the insole and a sensing module installed inside the insole. The sensing module is electrically coupled with the pressure sensing layer for receiving and processing detected electronic signals, where sensing module includes an inductance coil to perform wireless charging to the battery. The pressure sensing layer and the sensing module are integrally formed inside the insole.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Inventors: Yao-Sheng Chou, Hsiao-Yi Lin, Wei-Sheng Su, Hsing-Yu Chi
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Publication number: 20240071974Abstract: A semiconductor package includes a substrate and at least one integrated circuit (IC) die. Substrate solder resist has substrate solder resist openings exposing substrate bonding pads of the bonding surface of the substrate, and die solder resist has aligned die solder resist openings exposing die bonding pads of the bonding surface of the IC die. A ball grid array (BGA) electrically connects the die bonding pads with substrate bonding pads via the die solder resist openings and the substrate solder resist openings. The die solder resist openings include a subset A of the die solder resist openings in a region A of the bonding surface of the IC die and a subset B of the die solder resist openings in a region B of the bonding surface of the IC die. The die solder resist openings of subset A are larger than those of subset B.Type: ApplicationFiled: August 30, 2022Publication date: February 29, 2024Inventors: Yu-Sheng Lin, Chen-Nan Chiu, Jyun-Lin Wu, Yao-Chun Chuang
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Patent number: 10456084Abstract: An intelligent hospital bed may comprise a hospital bed, a first measuring unit, at least a second measuring unit, a third measuring unit, a central processor and a remote transmission device. The central processor is configured to receive signals from the measuring units and interpret the signals through comparison of data in a database of the central processor or a server. After interpreting, the central processor is configured to connect to the remote transmission device and send the interpreted information to a human-computer interaction through the remote transmission device such that the caregiver is able to master real-time conditions of patients respectively in the hospital beds including injection and urination status at the same time, thereby achieving the most effective allocation and utilization of care resource.Type: GrantFiled: August 2, 2018Date of Patent: October 29, 2019Assignees: Yung Hsiang Information Management, Co. Ltd, Dept. of Electrical Engineering, National Changhua University of EducationInventors: Yao-Sheng Lin, Tsair-Rong Chen, Yu-Lin Juan
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Patent number: 8247908Abstract: A circuit substrate and the method for fabricating a packaging of the circuit substrate are provided. A plurality of electrodes are formed on the surface of the circuit substrate, the electrodes are formed with fork structures over an connection section of the circuit substrate, so that when the circuit substrate expands/contracts due to thermal processes, the probability of alignment with electrodes of an external circuit board is increased by easily detaching the fork structure overlapping an electrode of the external circuit board which is not corresponding to the fork structure of the electrode of the circuit substrate, so as to avoid short circuit. Thus, electrode misalignment due to electrode pitch variation of the traditional circuit substrate as a result of thermal deformation can be effectively eliminated.Type: GrantFiled: July 26, 2010Date of Patent: August 21, 2012Assignee: Industrial Technology Research InstituteInventors: Yao-Sheng Lin, Tai-Hong Chen
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Patent number: 8023060Abstract: A flexible display including a flexible display panel and a flexible hollow supporting structure is provided. The flexible display panel has a first end and a second end opposite to each other. The flexible hollow supporting structure is integrated with the flexible display panel and extends from the first end to the second end of the flexible display panel. In addition, a supporting medium can be infused into the flexible hollow supporting structure so as to stretch and support the flexible display panel.Type: GrantFiled: October 28, 2007Date of Patent: September 20, 2011Assignee: Industrial Technology Research InstituteInventors: Yao-Sheng Lin, Tai-Hong Chen, Su-Yu Fun
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Patent number: 7988808Abstract: A bonding structure with a buffer layer, and a method of forming the same are provided. The bonding structure comprises a first substrate with metal pads thereon, a protection layer covered on the surface of the substrate, a first adhesive metal layer formed on the metal pads, a buffer layer coated on the protection layer and the metal pads, a first metal layer covered on the buffer layer, and a second substrate with electrodes and a bonding layer thereon. The first metal layer, the electrodes and the bonding layer are bonded to form the bonding structure. Direct bonding can be performed through surface activation or heat pressure. The method uses fewer steps and is more reliable. The temperature required for bonding the structure is lower. The bonding density between the contacted surfaces is increased to a fine pitch. The quality at the bonding points is increased because fewer contaminations between the contacted surfaces are generated.Type: GrantFiled: August 19, 2008Date of Patent: August 2, 2011Assignee: Industrial Technology Research InstituteInventors: Su-Tsai Lu, Shu-Ming Chang, Shyh-Ming Chang, Yao-Sheng Lin, Yuan-Chang Huang
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Publication number: 20100283159Abstract: A circuit substrate and the method for fabricating a packaging of the circuit substrate are provided. A plurality of electrodes are formed on the surface of the circuit substrate, the electrodes are formed with fork structures over an connection section of the circuit substrate, so that when the circuit substrate expands/contracts due to thermal processes, the probability of alignment with electrodes of an external circuit board is increased by easily detaching the fork structure overlapping an electrode of the external circuit board which is not corresponding to the fork structure of the electrode of the circuit substrate, so as to avoid short circuit. Thus, electrode misalignment due to electrode pitch variation of the traditional circuit substrate as a result of thermal deformation can be effectively eliminated.Type: ApplicationFiled: July 26, 2010Publication date: November 11, 2010Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yao-Sheng LIN, Tai-Hong CHEN
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Patent number: 7465603Abstract: A wafer level package structure of optical-electronic device and method for making the same are disclosed. The wafer level package structure of optical-electronic device is provided by employing a substrate whose surfaces have several optical sensitive areas and divided into individual package devices. The manufacture steps first involve providing a substrate with several chips whose surfaces have an optical sensitive area and bonding pads, and providing transparent layer whose surfaces have conductive circuits and scribe lines. Then the bonding pads bond to conductive circuits and a protection layer is formed on the chip to expose partly conductive circuits. Forming a conductive film on the protection layer and the conductive film contacts with the extending conductive circuits to form the wafer level package structure of optical-electronic device. At last, the transparent layer is diced according to scribe lines to form the individual package devices.Type: GrantFiled: November 13, 2007Date of Patent: December 16, 2008Assignee: Industrial Technology Research InstituteInventors: Yuan-Chang Huang, Tai-Hung Chen, Yao-Sheng Lin, Su-Tsai Lu
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Publication number: 20080305624Abstract: A bonding structure with a buffer layer, and a method of forming the same are provided. The bonding structure comprises a first substrate with metal pads thereon, a protection layer covered on the surface of the substrate, a first adhesive metal layer formed on the metal pads, a buffer layer coated on the protection layer and the metal pads, a first metal layer covered on the buffer layer, and a second substrate with electrodes and a bonding layer thereon. The first metal layer, the electrodes and the bonding layer are bonded to form the bonding structure. Direct bonding can be performed through surface activation or heat pressure. The method uses fewer steps and is more reliable. The temperature required for bonding the structure is lower. The bonding density between the contacted surfaces is increased to a fine pitch. The quality at the bonding points is increased because fewer contaminations between the contacted surfaces are generated.Type: ApplicationFiled: August 19, 2008Publication date: December 11, 2008Inventors: Su-Tsai Lu, Shu-Ming Chang, Shyh-Ming Chang, Yao-Sheng Lin, Yuan-Chang Huang
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Patent number: 7459055Abstract: A bonding structure with a buffer layer, and a method of forming the same are provided. The bonding structure comprises a first substrate with metal pads thereon, a protection layer covered on the surface of the substrate, a first adhesive metal layer formed on the metal pads, a buffer layer coated on the protection layer and the metal pads, a first metal layer covered on the buffer layer, and a second substrate with electrodes and a bonding layer thereon. The first metal layer, the electrodes and the bonding layer are bonded to form the bonding structure. Direct bonding can be performed through surface activation or heat pressure. The method uses fewer steps and is more reliable. The temperature required for bonding the structure is lower. The bonding density between the contacted surfaces is increased to a fine pitch. The quality at the bonding points is increased because fewer contaminations between the contacted surfaces are generated.Type: GrantFiled: October 16, 2006Date of Patent: December 2, 2008Assignee: Industrial Technology Research InstituteInventors: Su-Tsai Lu, Shu-Ming Chang, Shyh-Ming Chang, Yao-Sheng Lin, Yuan-Chang Huang
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Patent number: 7446421Abstract: A bonding structure with a buffer layer, and a method of forming the same are provided. The bonding structure comprises a first substrate with metal pads thereon, a protection layer covered on the surface of the substrate, a first adhesive metal layer formed on the metal pads, a buffer layer coated on the protection layer and the metal pads, a first metal layer covered on the buffer layer, and a second substrate with electrodes and a bonding layer thereon. The first metal layer, the electrodes and the bonding layer are bonded to form the bonding structure. Direct bonding can be performed through surface activation or heat pressure. The method uses fewer steps and is more reliable. The temperature required for bonding the structure is lower. The bonding density between the contacted surfaces is increased to a fine pitch. The quality at the bonding points is increased because fewer contaminations between the contacted surfaces are generated.Type: GrantFiled: January 4, 2007Date of Patent: November 4, 2008Assignee: Industrial Technology Research InstituteInventors: Su-Tsai Lu, Shu-Ming Chang, Shyh-Ming Chang, Yao-Sheng Lin, Yuan-Chang Huang
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Publication number: 20080198541Abstract: A flexible display including a flexible display panel and a flexible hollow supporting structure is provided. The flexible display panel has a first end and a second end opposite to each other. The flexible hollow supporting structure is integrated with the flexible display panel and extends from the first end to the second end of the flexible display panel. In addition, a supporting medium can be infused into the flexible hollow supporting structure so as to stretch and support the flexible display panel.Type: ApplicationFiled: October 28, 2007Publication date: August 21, 2008Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yao-Sheng Lin, Tai-Hong Chen, Su-Yu Fun
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Patent number: 7378746Abstract: A composite bump suitable for disposing on a substrate pad is provided. The composite bump includes a compliant body and an outer conductive layer. The coefficient of thermal expansion (CTE) of the compliant body is between 5 ppm/° C. and 200 ppm/° C. The outer conductive layer covers the compliant body and is electrically connected to the pad. The compliant body can provide a stress buffering effect for a bonding operation. Furthermore, by setting of the CTE of the compliant body within a preferable range, damages caused by thermal stress are reduced while the bonding effect is enhanced.Type: GrantFiled: March 10, 2006Date of Patent: May 27, 2008Assignee: Industrial Technology Research InstituteInventors: Ji-Cheng Lin, Yao-Sheng Lin, Shyh-Ming Chang, Su-Tsai Lu, Hsien-Chie Cheng, Tai-Hong Chen
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Publication number: 20080081395Abstract: A wafer level package structure of optical-electronic device and method for making the same are disclosed. The wafer level package structure of optical-electronic device is provided by employing a substrate whose surfaces have several optical sensitive areas and divided into individual package devices. The manufacture steps first involve providing a substrate with several chips whose surfaces have an optical sensitive area and bonding pads, and providing transparent layer whose surfaces have conductive circuits and scribe lines. Then the bonding pads bond to conductive circuits and a protection layer is formed on the chip to expose partly conductive circuits. Forming a conductive film on the protection layer and the conductive film contacts with the extending conductive circuits to form the wafer level package structure of optical-electronic device. At last, the transparent layer is diced according to scribe lines to form the individual package devices.Type: ApplicationFiled: November 13, 2007Publication date: April 3, 2008Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yuan-Chang Huang, Tai-Hung Chen, Yao-Sheng Lin, Su-Tsai Lu
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Patent number: 7317235Abstract: A wafer level package structure of optical-electronic device and method for making the same are disclosed. The wafer level package structure of optical-electronic device is provided by employing a substrate whose surfaces have several optical sensitive areas and divided into individual package devices. The manufacture steps first involve providing a substrate with several chips whose surfaces have an optical sensitive area and bonding pads, and providing transparent layer whose surfaces have conductive circuits and scribe lines. Then the bonding pads bond to conductive circuits and a protection layer is formed on the chip to expose partly conductive circuits. Forming a conductive film on the protection layer and the conductive film contacts with the extending conductive circuits to form the wafer level package structure of optical-electronic device. At last, the transparent layer is diced according to scribe lines to form the individual package devices.Type: GrantFiled: March 18, 2005Date of Patent: January 8, 2008Assignee: Industrial Technology Research InstituteInventors: Yuan-Chang Huang, Tai-Hung Chen, Yao-Sheng Lin, Su-Tsai Lu