Abstract: A display substrate and a display apparatus. The display substrate includes sub-pixels. An orthographic projection of a first anode structure overlaps that of a first pixel driving circuit to form a first overlapping region. An orthographic projection of a second anode structure overlaps that of a second pixel driving circuit to form a second overlapping region. An area of the first overlapping region is less than that of the second overlapping region. The orthographic projection of the first anode structure overlaps that of a driving gate conductive portion of the first pixel driving circuit to form a third overlapping region. The orthographic projection of the second anode structure overlaps that of a driving gate conductive portion of the second pixel driving circuit to form a fourth overlapping region. A ratio of an area of the third overlapping region to that of the fourth overlapping region ranges from 0.8 to 1.2.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.

Abstract: A pixel circuit and a driving method thereof, a display substrate and a display device are provided. The pixel circuit includes a driving sub-circuit, a first switch sub-circuit and a first light-emitting control sub-circuit. The driving sub-circuit includes a control terminal connected with a first node, a first terminal connected with a second node and a second terminal connected with a third node, and is configured to control a driving signal from the first node to the third node for driving a light-emitting element; the first switch sub-circuit is configured to control conduction of the driving signal between the third node and a fourth node; the first light-emitting control sub-circuit is connected with a first electrode of the light-emitting element through a fifth node, and is configured to control conduction of the driving signal between the fourth node and the fifth node.

Abstract: An array substrate, an opposite substrate and a display panel are provided. The array substrate comprises: a display region and a periphery region surrounding the display region, wherein the display region comprises a plurality of pixel regions, and each of the pixel regions comprises a reflective region and a transmissive region; the reflective region comprises a driving signal outputting layer, a segment gap layer, a passivation layer and a reflective layer, the reflective layer is coupled to the driving signal outputting layer to enable both the reflective layer and the driving signal outputting layer to function as a reflective region driving electrode; the transmissive region comprises a first electrode layer, the first electrode layer is coupled to the driving signal outputting layer, the passivation layer extends to the transmissive region, and the passivation layer is arranged between the first electrode layer and a first base of the display substrate.

Abstract: An array substrate includes a first substrate; and a first electrode and a second electrode disposed on the first substrate and located in a sub-pixel region. At least one of the first electrode and the second electrode includes a plurality of electrode strips. Every two adjacent electrode strips in the first electrode and the second electrode have a slit therebetween. The slit includes a first end portion, a straight portion, and a second end portion connected in sequence. A bend is formed at a connection position of the first end portion and the straight portion, and the second end portion is formed by protruding from the straight portion. The straight portion includes a first edge and a second edge parallel to each other, and an average width of the first end portion in a direction perpendicular to the first edge is less than a width of the straight portion.

Abstract: Provided herein is a potassium-binding polymer prepared by polymerization reaction of a monomer and a crosslinking agent, wherein the monomer is the compound of formula (V), the crosslinking agent is the compound of formula (VI), and/or the compound of formula (VII), wherein the variables are as defined in the specification; to the use thereof for treating or preventing hyperkalemia.

Abstract: The present disclosure belongs to the technical field of wastewater treatment, and discloses an electrochemical nitrogen and phosphorus removal device and a method.

Abstract: Machine learning is used to train a network to estimate a three-dimensional (3D) body surface and body regions of a patient from surface images of the patient. The estimated 3D body surface of the patient is used to determine an isocenter of the patient. The estimated body regions are used to generate heatmaps representing visible body region boundaries and unseen body region boundaries of the patient. The estimation of 3D body surfaces, the determined patient isocenter, and the estimated body region boundaries may assist in planning a medical scan, including automatic patient positioning.

Abstract: A filament forming method includes: performing first stage to apply first bias including gate and drain voltages to a resistive memory unit plural times until read current reaches first saturating state, latching read current in first saturating state as saturating read current, determining whether rate of increase of saturating read current is less than first threshold value; when rate of increase of saturating read current is not less than first threshold value, performing second stage to apply second bias, by increasing gate voltage and decreasing drain voltage, to the resistive memory unit plural times until read current reaches second saturating state, latching read current in second saturating state as saturating read current and determining whether rate of increase of saturating read current is less than first threshold value; finishing the method when rate of increase of saturating read current is less than first threshold value and saturating read current reaches target current value.

Abstract: A method and system for identifying bonding between a material and tubing. The method may include disposing an acoustic logging tool in a wellbore, wherein the acoustic logging tool comprises a transmitter, a receiver, or a transceiver, broadcasting a shaped signal with the transmitter such that the shaped signal interacts with a boundary of a casing and a material and recording a result signal from the boundary with the receiver. The method may further comprise identifying a cut-off time to be applied to the result signal, transforming the result signal from a time domain to a frequency domain, selecting one or more modes sensitive to a bonding at the boundary between the casing and the material, computing a decay rate of the one or more modes that were selected based at least one or more decay curves, and converting the decay rate to a bonding log.

Abstract: Semiconductor devices and methods of manufacture which utilize lids in order to constrain thermal expansion during annealing are presented. In some embodiments lids are placed and attached on encapsulant and, in some embodiments, over first semiconductor dies. As such, when heat is applied, and the encapsulant attempts to expand, the lid will work to constrain the expansion, reducing the amount of stress that would otherwise accumulate within the encapsulant.

Abstract: A pixel arrangement structure includes: first sub-pixels, second sub-pixels and third sub-pixels, being not overlapped but being spaced apart. The third sub-pixel includes a first edge facing the first sub-pixel, the first sub-pixel includes a second edge facing the third sub-pixel, the third sub-pixel includes a third edge facing the second sub-pixel, and the second sub-pixel includes a fourth edge facing the third sub-pixel, and shapes of the first sub-pixel and the second sub-pixel are circles, the first edge and the second edge are curved edges with a same curvature, the third edge and the fourth edge are curved edges with a same curvature; or shapes of the first sub-pixel and the second sub-pixel are octagons, at least part of the first edge is parallel to at least part of the second edge, at least part of the third edge is parallel to at least part of the fourth edge.

Abstract: An impact-resistant polypropylene film and a method for producing the same are provided. The impact-resistant polypropylene film includes two outer layers and a middle layer. Each of the outer layers includes a propylene block polymer. The propylene block polymer includes a propylene monomer and an ethylene-propylene polymer, and the ethylene-propylene polymer is dispersed in the propylene monomer to form a sea-island structure. The sea-island structure includes a sea phase and an island phase, the propylene monomer is defined as the sea phase, and the ethylene-propylene polymer is defined as the island phase. The middle layer includes a propylene block polymer and an ethylene elastomer. Based on 100 parts by weight of the middle layer, a content of the propylene block polymer is 60 to 80 parts by weight, and a content of the ethylene elastomer is 20 to 40 parts by weight.

Abstract: A semiconductor light-emitting device includes a semiconductor stack including a first semiconductor layer and a second semiconductor layer; a first reflective layer formed on the first semiconductor layer and including a plurality of vias; a plurality of contact structures respectively filled in the vias and electrically connected to the first semiconductor layer; a second reflective layer including metal material formed on the first reflective layer and contacting the contact structures; a plurality of conductive vias surrounded by the semiconductor stack; a connecting layer formed in the conductive vias and electrically connected to the second semiconductor layer; a first pad portion electrically connected to the second semiconductor layer; and a second pad portion electrically connected to the first semiconductor layer, wherein a shortest distance between two of the conductive vias is larger than a shortest distance between the first pad portion and the second pad portion.

Abstract: A multi-chip interconnection package structure with a heat dissipation plate and a preparation method thereof are provided. The multi-chip interconnection package structure with a heat dissipation plate includes a fine circuit layer, at least one die, a heat dissipation plate, a plastic package body, and a package circuit layer, the heat dissipation plate is provided on the fine circuit layer, and is mounted on a side of the die away from the fine circuit layer, the plastic package body wraps the die and the heat dissipation plate, and the package circuit layer is provided on the plastic package body.

Abstract: A multi-chip device includes a first material within a substrate. The first material has a first coefficient of thermal expansion different than a second coefficient of thermal expansion of the substrate. A first chip overlies a first portion of the first material and a first portion of the substrate. A second chip overlies a second portion of the first material and a second portion of the substrate. The first material is between the first portion of the substrate and the second portion of the substrate.

Abstract: Embodiments of the present application provide a case of a battery, a battery, a power consumption device, and a method and device for preparing a battery. The case includes: an electrical chamber configured to accommodate a plurality of battery cells and a bus component, where at least one battery cell of the plurality of battery cells includes a pressure relief mechanism; a thermal management component configured to accommodate a fluid to adjust temperatures of the plurality of battery cells; and a collection chamber configured to collect, when the pressure relief mechanism is actuated, emissions from the battery cell provided with the pressure relief mechanism; where the thermal management component is configured to isolate the electrical chamber from the collection chamber. According to the technical solutions of the embodiments of the present application, the safety of the battery can be enhanced.

Abstract: A display substrate and a display device are provided. The display substrate includes a display region, at least one first signal line, and at least one connecting wire. The display region includes a first display region and a second display region; the first display region includes at least one first light emitting element, and the second display region includes at least one first pixel circuit; the first signal line includes a first main body portion and a first winding portion; the first main body portion extends along a first direction, and at least part of the first winding portion extends along a direction intersecting with the first direction; at least one first signal line is electrically connected to at least one first pixel circuit; and at least one first pixel circuit is configured to respectively drive at least one first light emitting element.

Abstract: A method includes receiving a wafer, measuring a surface topography of the wafer; calculating a topographical variation based on the surface topography measurement performing a single-zone alignment compensation when the topographical variation is less than a predetermined value or performing a multi-zone alignment compensation when the topographical variation is greater than the predetermined value; and performing a wafer alignment according to the single-zone alignment compensation or the multi-zone alignment compensation.

Abstract: Some embodiments relate to a semiconductor structure. The semiconductor structure includes a first substrate including a first plurality of conductive pads that are laterally spaced apart from one another on the first substrate. A first plurality of conductive bumps are disposed on the first plurality of conductive pads, respectively. A multi-tiered solder-resist structure is disposed on the first substrate and arranged between the first plurality of conductive pads. The multi-tiered solder-resist structure has different widths at a different heights over the first substrate and contacts sidewalls of the first plurality of conductive bumps to separate the first plurality of conductive bumps from one another.