Abstract: An improved charge pump design is disclosed. This charge pump comprises at least one pumping transistor having a triple well arrangement. This triple pump transistor has a source and a drain region of a first conductive type formed on a first well having an opposite conductive type. A second well having the first conductive type is formed outside of the first well. The source region, first well and second well are set to substantially the same potential. One aspect of this configuration is that the first well forms a semiconductor diode with the drain region. Another aspect of this arrangement is that the body effect of the transistor is reduced. The reduction in body effect reduces the threshold voltage of the transistor. It is found that the above mentioned diode and threshold voltage reduction, singly and in combination, allow the charge pump to operate more efficiently.

Abstract: A user-programmable write protection scheme provides flexibility and superior write protect features for an integrated circuit memory which comprises an array of non-volatile erasable and programmable memory cells, including a plurality of sectors. Command logic detects command sequences indicating operations for the array, including a program operation, a sector erase operation, a read operation, a sector lock operation, and a sector unlock operation. The sector protect logic includes sector lock memory, including non-volatile memory cells that store sector lock signals for at least one sector in the array.

Abstract: A new flash memory cell structure and operational bias is based on the use of a triple well flash memory cell which allows pre-programming by Fowler Nordheim (F-N) tunneling over blocks of cells at a time. The floating gate memory cell is made in a semiconductor substrate having a first conductivity type, such as p-type. A first well within the substrate by having a second conductivity type different than the first conductivity type is included. A second well within the first well is also included having the first conductivity type. A drain and a source are formed in the second well having the second conductivity type, and spaced away from one another to define a channel area between the drain and the source. A floating gate and control gate structure is included over the channel area.

Abstract: A floating gate memory with a protocol which terminates a program load cycle upon detecting a predetermined address and/or data pattern, providing positive indication of the end of the load cycle, and eliminating the requirement for a long pulse in a controlled signal. Command logic executes a process to store a block of data in response to a sequence of addresses and data segments received at the input/output circuitry, and detects the last segment in a block of data in response to a pattern including at least one of the addresses and data segments received at the input/output circuitry. One pattern includes consecutive matching addresses. Pattern match logic included in the command logic is coupled to the input/output circuitry and stores addresses in the sequence and compares them with a next address to indicate a matching address. Alternatively, the pattern includes both matching addresses and data segments with corresponding comparator circuitry.

Abstract: An array (10) of multi-level floating gate memory cells includes wordlines (18) connected to memory cells along a row in the array, and bit lines (12) connected to memory cells along a column in the array. A wordline voltage source (27) is included which supplies selectively wordline voltages corresponding to respective threshold voltages of the memory cells in the array. A plurality of bit latches form a page buffer (11). Bit latches are coupled to corresponding bit lines, and have a first state and a second state. The bit latches include circuits (213-216) to change the bit latches from the first state to the second state in response to signals on the corresponding bit lines that are generated in response to a wordline voltage on a selected wordline being greater than or equal to the threshold voltage of a memory cell on the corresponding bit line connected to the selected wordline.

Abstract: A flexible technique for improving yield of manufacturing of high density of memory devices, such as flash EEPROM, involves reconfiguring an integrated circuit memory array having a plurality of sectors selected by an address decoder in response to an N bit field in an address. If defective sectors are detected in the array, it is partitioned to disable defective sectors by configuring a sector decoder to prevent access to the defective sectors while maintaining sequential addressing remaining sectors in the array. The step of partitioning includes configuring the sector decoder to replace a defective sector in one half of the array by another sector in the other half of the array having N-m of the N address bits in common with the defective sector when m is between 1 and N-1.

Abstract: Wordline driver circuitry drives a plurality of wordlines in a flash EEPROM memory array in a first mode which selects between a positive voltage and ground, and a second mode which selects between a negative voltage and ground. A first supply voltage selector supplies positive voltage during the first mode, and a second mode reference voltage, such as ground, in the second mode. A second supply voltage selector supplies the first mode reference voltage such as ground in the first mode, and the negative voltage during a second mode. An inverting driver has an input which receives a wordline select signal, and an output coupled to the wordline, a first supply voltage input connected to the first supply voltage selector, and second supply voltage input connected to the second supply voltage selector.