Patents by Inventor Yao-Yu Lee

Yao-Yu Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11990258
    Abstract: An over-current protection device includes first and second electrode layers and a PTC material layer laminated therebetween. The PTC material layer includes a polymer matrix, a conductive filler, and a titanium-containing dielectric filler. The polymer matrix has a fluoropolymer. The titanium-containing dielectric filler has a compound represented by a general formula of MTiO3, wherein the M represents transition metal or alkaline earth metal. The total volume of the PTC material layer is calculated as 100%, and the titanium-containing dielectric filler accounts to for 5-15% by volume of the PTC material layer.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: May 21, 2024
    Assignee: POLYTRONICS TECHNOLOGY CORP.
    Inventors: Hsiu-Che Yen, Yung-Hsien Chang, Cheng-Yu Tung, Chen-Nan Liu, Chia-Yuan Lee, Yu-Chieh Fu, Yao-Te Chang, Fu-Hua Chu
  • Publication number: 20240145132
    Abstract: An over-current protection device includes first and second electrode layers and a PTC material layer laminated therebetween. The PTC material layer includes a polymer matrix, and a conductive filler. The polymer matrix has a fluoropolymer. The total volume of the PTC material layer is calculated as 100%, and the fluoropolymer accounts for 47-62% by volume of the PTC material layer. The fluoropolymer has a melt viscosity higher than 3000 Pa·s.
    Type: Application
    Filed: March 16, 2023
    Publication date: May 2, 2024
    Inventors: CHENG-YU TUNG, CHEN-NAN LIU, Chia-Yuan Lee, HSIU-CHE YEN, YUNG-HSIEN CHANG, Yao-Te Chang, FU-HUA CHU
  • Publication number: 20240145133
    Abstract: An over-current protection device includes a first metal layer, a second metal layer and a heat-sensitive layer laminated therebetween. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic and includes a polymer matrix and a first conductive filler. The polymer matrix includes a polyolefin-based polymer and a fluoropolymer. The fluoropolymer has a melt flow index higher than 1.9 g/10 min, and the polyolefin-based polymer and the fluoropolymer together form an interpenetrating polymer network (IPN). The first conductive filler has a metal-ceramic compound dispersed in the polymer matrix.
    Type: Application
    Filed: April 5, 2023
    Publication date: May 2, 2024
    Inventors: CHEN-NAN LIU, YUNG-HSIEN CHANG, CHENG-YU TUNG, HSIU-CHE YEN, Chia-Yuan LEE, Yao-Te CHANG, FU-HUA CHU
  • Patent number: 11967570
    Abstract: A semiconductor package includes a base comprising a top surface and a bottom surface that is opposite to the top surface; a first semiconductor chip mounted on the top surface of the base in a flip-chip manner; a second semiconductor chip stacked on the first semiconductor chip and electrically coupled to the base by wire bonding; an in-package heat dissipating element comprising a dummy silicon die adhered onto the second semiconductor chip by using a high-thermal conductive die attach film; and a molding compound encapsulating the first semiconductor die, the second semiconductor die, and the in-package heat dissipating element.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: April 23, 2024
    Assignee: MediaTek Inc.
    Inventors: Chia-Hao Hsu, Tai-Yu Chen, Shiann-Tsong Tsai, Hsing-Chih Liu, Yao-Pang Hsu, Chi-Yuan Chen, Chung-Fa Lee
  • Publication number: 20240127988
    Abstract: An over-current protection device includes a first metal layer, a second metal layer and a heat-sensitive layer laminated therebetween. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic and includes a first polymer and a conductive filler. The first polymer consists of polyvinylidene difluoride (PVDF), and PVDF exists in different phases such as ?-PVDF, ?-PVDF and ?-PVDF. The total amount of ?-PVDF, ?-PVDF and ?-PVDF is calculated as 100%, and the amount of ?-PVDF accounts for 48% to 55%. The conductive filler has a metal-ceramic compound.
    Type: Application
    Filed: March 2, 2023
    Publication date: April 18, 2024
    Inventors: HSIU-CHE YEN, YUNG-HSIEN CHANG, CHENG-YU TUNG, Chia-Yuan Lee, CHEN-NAN LIU, Yao-Te Chang, FU-HUA CHU
  • Publication number: 20240127989
    Abstract: An over-current protection device includes a first metal layer, a second metal layer and a heat-sensitive layer laminated therebetween. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic and includes a first polymer and a conductive filler. The first polymer consists of polyvinylidene difluoride (PVDF), and PVDF exists in different phases such as ?-PVDF, ?-PVDF and ?-PVDF. The total amount of ?-PVDF, ?-PVDF and ?-PVDF is calculated as 100%, and the amount of ?-PVDF accounts for 33% to 42%.
    Type: Application
    Filed: January 25, 2023
    Publication date: April 18, 2024
    Inventors: CHIA-YUAN LEE, CHENG-YU TUNG, HSIU-CHE YEN, CHEN-NAN LIU, YUNG-HSIEN CHANG, YAO-TE CHANG, FU-HUA CHU
  • Patent number: 7450482
    Abstract: A method for optimizing write parameters of an optical storage medium is provided. The method is adapted for a recording device using the optical storage medium. The method includes loading the optical storage medium having a test area into the recording device, determining a combination of an original write strategy and an original write power according to the optical storage medium, writing test data into the test area with the combination of the original write strategy and the original write power for dynamically adjusting the combination of the original write strategy and the original write power to obtain a combination of an optimal write strategy and an optimal write power, and writing data into the optical storage medium with the combination of the optimal write strategy and the optimal write power.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: November 11, 2008
    Assignee: Sunplus Technology Co., Ltd.
    Inventors: Yao-Yu Lee, Hsin-Po Wang, Yueh-Hsuan Tsai
  • Publication number: 20070127331
    Abstract: A layer jump control apparatus and method is provided to control an optical drive during a layer jump operation. According to the magnitude variations of a focus error signal during a predetermined period, the invention estimates the position and relative velocity of a pickup head and a disk so as to dynamically modify the magnitude of a braking force, causing the optical pickup head to make a stable jump on the target layer, then brake and finally reactivate a closed-loop focus control process without going into an out of lock state.
    Type: Application
    Filed: December 6, 2006
    Publication date: June 7, 2007
    Inventors: Yao-Yu Lee, Ching-Chuan Chen, Jung-Huang Huang
  • Publication number: 20070041293
    Abstract: A method for optimizing write parameters of an optical storage medium is provided. The method is adapted for a recording device using the optical storage medium. The method includes loading the optical storage medium having a test area into the recording device, determining a combination of an original write strategy and an original write power according to the optical storage medium, writing test data into the test area with the combination of the original write strategy and the original write power for dynamically adjusting the combination of the original write strategy and the original write power to obtain a combination of an optimal write strategy and an optimal write power, and writing data into the optical storage medium with the combination of the optimal write strategy and the optimal write power.
    Type: Application
    Filed: November 22, 2005
    Publication date: February 22, 2007
    Inventors: Yao-Yu Lee, Hsin-Po Wang, Yueh-Hsuan Tsai
  • Patent number: 6274992
    Abstract: The specification discloses a braking method for a single-phase motor, which is applied to a single-phase DC brushless motor driven by a three-phase motor driving IC. The invention uses a control unit to compute the rotational speed of the single-phase motor according to a rotation number signal generated by the motor rotational axis. When the rotational speed is below a threshold, the motor driving IC is controlled to stop rotating the single-phase motor. Through the single-phase motor braking method disclosed herein, the problem of unable to determine the rotational direction of a single-phase motor within a three-phase motor driving IC existing in the prior art can be solved by merely modifying the program in the control unit without adding system elements.
    Type: Grant
    Filed: August 17, 2000
    Date of Patent: August 14, 2001
    Assignee: Industrial Technology Research Institute
    Inventors: King Yin Wang, Li-Te Kuo, Yao-Yu Lee, Ming-Jiou Yu, Der-Ray Huaug
  • Patent number: 6232619
    Abstract: A design of a test chip for determining the dopant uniformity of an ion implantation within a area of the order of several tens of microns is disclosed and a method for it's measurement provided. The object of the test chip is particularly adapted to sense dopant concentration variations caused by the variation of density in the spot of the ion implantation beam and can be used to determine optimal overlap of adjacent beam scans. The test chips use arrays of MOSFETs arranged in a pattern with channel lengths parallel to the path of the ion implantation beam and provide a contiguous set of incremental concentration measurements across the paths of the ion implantation beam scans. The gate threshold voltages are measured and related to the active dopant impurity concentration in the channel area. The width of the concentration increment is therefore equal to the channel length.
    Type: Grant
    Filed: June 26, 2000
    Date of Patent: May 15, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chien-Fong Chen, Yao-Yu Lee
  • Patent number: 6107108
    Abstract: A design of a test chip for determining the dopant uniformity of an ion implantation within a area of the order of several tens of microns is disclosed and a method for it's measurement provided. The object of the test chip is particularly adapted to sense dopant concentration variations caused by the variation of density in the spot of the ion implantation beam and can be used to determine optimal overlap of adjacent beam scans. The test chips use arrays of MOSFETs arranged in a pattern with channel lengths parallel to the path of the ion implantation beam and provide a contiguous set of incremental concentration measurements across the paths of the ion implantation beam scans. The gate threshold voltages are measured and related to the active dopant impurity concentration in the channel area. The width of the concentration increment is therefore equal to the channel length.
    Type: Grant
    Filed: August 14, 1998
    Date of Patent: August 22, 2000
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chien-Fong Chen, Yao-Yu Lee