Patents by Inventor Yaohua Zhu

Yaohua Zhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Hierarchical ROM encoder system for performing address fault detection in a memory system
    Patent number: 11798644
    Abstract: Various embodiments are disclosed for performing address fault detection in a memory system using a hierarchical ROM encoding system. In one embodiment, a hierarchical ROM encoding system comprises two levels of ROM encoders that are used to detect an address fault. In another embodiment, a hierarchical ROM encoding system comprises three levels of ROM encoders that are used to detect an address fault.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: October 24, 2023
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Xiaozhou Qian, Yaohua Zhu
  • Hierarchical ROM Encoder System For Performing Address Fault Detection In A Memory System
    Publication number: 20230170035
    Abstract: Various embodiments are disclosed for performing address fault detection in a memory system using a hierarchical ROM encoding system. In one embodiment, a hierarchical ROM encoding system comprises two levels of ROM encoders that are used to detect an address fault. In another embodiment, a hierarchical ROM encoding system comprises three levels of ROM encoders that are used to detect an address fault.
    Type: Application
    Filed: February 11, 2022
    Publication date: June 1, 2023
    Inventors: Xiaozhou Qian, YAOHUA ZHU
  • Non-volatile memory system using strap cells in source line pull down circuits
    Patent number: 11508442
    Abstract: The present invention relates to a flash memory device that uses strap cells in a memory array of non-volatile memory cells as source line pull down circuits. In one embodiment, the strap cells are erase gate strap cells. In another embodiment, the strap cells are source line strap cells. In another embodiment, the strap cells are control gate strap cells. In another embodiment, the strap cells are word line strap cells.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: November 22, 2022
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Leo Xing, Chunming Wang, Xian Liu, Nhan Do, Guangming Lin, Yaohua Zhu
  • Non-volatile Memory System Using Strap Cells In Source Line Pull Down Circuits
    Publication number: 20210327512
    Abstract: The present invention relates to a flash memory device that uses strap cells in a memory array of non-volatile memory cells as source line pull down circuits. In one embodiment, the strap cells are erase gate strap cells. In another embodiment, the strap cells are source line strap cells. In another embodiment, the strap cells are control gate strap cells. In another embodiment, the strap cells are word line strap cells.
    Type: Application
    Filed: October 19, 2020
    Publication date: October 21, 2021
    Inventors: Leo XING, Chunming WANG, Xian LIU, Nhan DO, Guangming LIN, Yaohua ZHU
  • High speed and low power sense amplifier
    Patent number: 9997252
    Abstract: An improved sensing circuit is disclosed that utilizes a bit line in an unused memory array to provide reference values to compare against selected cells in another memory array. A circuit that can perform a self-test for identifying bit lines with leakage currents about an acceptable threshold also is disclosed.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: June 12, 2018
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Xiao Yan Pi, Xiaozhou Qian, Kai Man Yue, Yao Zhou, Yaohua Zhu
  • High Speed And Low Power Sense Amplifier
    Publication number: 20180005701
    Abstract: An improved sensing circuit is disclosed that utilizes a bit line in an unused memory array to provide reference values to compare against selected cells in another memory array. A circuit that can perform a self-test for identifying bit lines with leakage currents about an acceptable threshold also is disclosed.
    Type: Application
    Filed: September 15, 2017
    Publication date: January 4, 2018
    Inventors: Xiao Yan Pi, Xiaozhou Qian, Kai Man Yue, Yao Zhou, Yaohua Zhu
  • High Speed And Low Power Sense Amplifier
    Publication number: 20160254060
    Abstract: An improved sensing circuit is disclosed that utilizes a bit line in an unused memory array to provide reference values to compare against selected cells in another memory array. A circuit that can perform a self-test for identifying bit lines with leakage currents about an acceptable threshold also is disclosed.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 1, 2016
    Inventors: XIAO YAN PI, XIAOZHOU QIAN, KAI MAN YUE, YAO ZHOU, YAOHUA ZHU
  • Bitline regulator for high speed flash memory system
    Patent number: 9378834
    Abstract: A bitline regulator for use in a high speed flash memory system is disclosed. The bitline regulator is responsive to a set of trim bits that are generated by comparing the bias voltage of a bitline to a reference voltage.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: June 28, 2016
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Xiaozhou Qian, Yao Zhou, Bin Sheng, Jiaxu Peng, Yaohua Zhu
  • Bitline Regulator For High Speed Flash Memory System
    Publication number: 20160027519
    Abstract: A bitline regulator for use in a high speed flash memory system is disclosed. The bitline regulator is responsive to a set of trim bits that are generated by comparing the bias voltage of a bitline to a reference voltage.
    Type: Application
    Filed: September 15, 2014
    Publication date: January 28, 2016
    Inventors: Xiaozhou Qian, Yao Zhou, Bin Sheng, Jiaxu Peng, Yaohua Zhu