Abstract: In a virtual-machine system running on a supercomputer wherein a vector processor is shared among a plurality of operating systems/virtual machines enhancing of the efficiency of a system as a whole is provided. When an activation, status-test or set-up instruction of a vector processor 2 is executed while an OS is running on a scalar processor 1 with an interception flag 7 set to the logic value 1, an exception is generated, canceling the execution of the instruction. In the processing of the interception, whether the logic value of the interception flag is 1 and whether the instruction giving rise to the exception is an activation, status-test or set-up instruction of the vector processor 2 are examined. If the logic value is 1 and the activation, status-test or set-up instruction is verified, an interception is carried out. The virtual-machine monitor emulates the end-interrupt processing of the vector processor, allowing the utilization efficiency of the vector processor to be increased.

Abstract: The vector processing apparatus fetches vector operands designated by an instruction from a storage to an operand buffer in a vector processor. The vector processor reads out and processes the elements of the vector operands stored in the operand buffer. The vector processor controls fetching of the element to be next processed from the operand buffer in accordance with the operation result. Thus, a vector operation of a type in which the increment of the indices of the vector operands depends on the operation result is carried out.