Patents by Inventor Yarema A. Hryciw

Yarema A. Hryciw has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus and method for management of integrated circuit layout verification processes
    Patent number: 6115546
    Abstract: An apparatus and method for managing data obtained during the Design Rule Check (DRC) and Layout versus Schematic (LVS) verification procedures executed during the design of an integrated circuit. The apparatus is a data processing system which includes a database containing information regarding the schematics and layouts of the cells of an integrated circuit. The system accesses the database upon the completion of a DRC or LVS operation and queries the user as to whether the cell should be marked as successfully passing the appropriate verification procedure. A user is also able to access a report generating module to inspect the verification status of a cell in the IC design and generate a report showing the status of the verification procedures for each cell, organized according to one of several criteria.
    Type: Grant
    Filed: July 22, 1998
    Date of Patent: September 5, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Christophe J. Chevallier, Yarema A. Hryciw
  • Apparatus and method for management of integrated circuit layout verification processes
    Patent number: 5787006
    Abstract: An apparatus and method for managing data obtained during the Design Rule Check (DRC) and Layout versus Schematic (LVS) verification procedures executed during the design of an integrated circuit. The apparatus is a data processing system which includes a database containing information regarding the schematics and layouts of the cells of an integrated circuit. The system accesses the database upon the completion of a DRC or LVS operation and queries the user as to whether the cell should be marked as successfully passing the appropriate verification procedure. A user is also able to access a report generating module to inspect the verification status of a cell in the IC design and generate a report showing the status of the verification procedures for each cell, organized according to one of several criteria.
    Type: Grant
    Filed: April 30, 1996
    Date of Patent: July 28, 1998
    Assignee: Micron Technology, Inc.
    Inventors: Christophe J. Chevallier, Yarema A. Hryciw