Abstract: The present disclosure is directed to a network processor for processing high volumes of traffic provided by todays access networks at (or near) wireline speeds. The network process can be implemented within a residential gateway to perform, among other functions, routing to deliver high speed data services (e.g., data services with rates up to 10 Gbit/s) from a wide area network (WAN) to end user devices in a local area network (LAN).

Abstract: The present disclosure is directed to a network processor for processing high volumes of traffic provided by todays access networks at (or near) wireline speeds. The network process can be implemented within a residential gateway to perform, among other functions, routing to deliver high speed data services (e.g., data services with rates up to 10 Gbit/s) from a wide area network (WAN) to end user devices in a local area network (LAN).

Abstract: The Optical line terminal (OLT) tracks the number of data packets, bandwidth per user, and other data packet statistics. DDR (DRAM) is used to store the information tracked by the OLT. The DDR is accessed in a burst mode. In particular, the data is initially stored in an on-chip cache memory and then the data is sent periodically to the DDR in a burst mode. Leaky buckets can be used for each flow, and time stamps can be used to determine the last time the bucket was accessed.

Abstract: A network processor for performing residential gateway processing tasks. The network processor includes a first cluster of packet processors and a second cluster of packet processors, wherein each of the first cluster and the second cluster includes a main packet processor and a secondary packet processor, wherein the main packet processor performs at least routing of incoming packets and the secondary packet processor performs off-loading tasks for the main packet processor; a plurality of Ethernet media access control (MAC) adapters for interfacing with a plurality of subscriber devices connected to a residential gateway; an external-network MAC adapter for interfacing with a wide area network (WAN) connected to the network processor; and an ingress handler for at least load balancing the processing of packets between the first cluster and the second cluster.

Abstract: A frequency adapter for synchronizing data transfers between a low-frequency module and a high-frequency module connected to an internal bus. The frequency adapter includes a low-to-high synchronization unit for synchronizing data transfers from the low frequency module to the high-frequency module, wherein the low-to-high synchronization unit is clocked by a low frequency clock; and a high-to-low synchronization unit for synchronizing data transfers from the high frequency module to the low-frequency module, wherein the high-to-low synchronization unit is clocked by a low frequency clock.

Abstract: A network processor for performing residential gateway processing tasks. The network processor includes a first cluster of packet processors and a second cluster of packet processors, wherein each of the first cluster and the second cluster includes a main packet processor and a secondary packet processor, wherein the main packet processor performs at least routing of incoming packets and the secondary packet processor performs off-loading tasks for the main packet processor; a plurality of Ethernet media access control (MAC) adapters for interfacing with a plurality of subscriber devices connected to a residential gateway; an external-network MAC adapter for interfacing with a wide area network (WAN) connected to the network processor; and an ingress handler for at least load balancing the processing of packets between the first cluster and the second cluster.

Abstract: A frequency adapter for synchronizing data transfers between a low-frequency module and a high-frequency module connected to an internal bus. The frequency adapter includes a low-to-high synchronization unit for synchronizing data transfers from the low frequency module to the high-frequency module, wherein the low-to-high synchronization unit is clocked by a low frequency clock; and a high-to-low synchronization unit for synchronizing data transfers from the high frequency module to the low-frequency module, wherein the high-to-low synchronization module is clocked by a low frequency clock.