Patents by Inventor Yasir Sulehria
Yasir Sulehria has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230386897Abstract: A microelectronics device including a gate region located adjacent to a source/drain region. A contact located above the source/drain region, where the contact has a bottom section, a middle section and top section, wherein the sidewalls of the bottom section, the middle section, and the top section of the contact are tapered towards a center Y-axis of the contact. A gate contact located above the gate region, where the gate contact has tapered sidewalls towards a center Y-axis of the gate contact. The gate contact is adjacent to the contact. The tapering of the sidewalls of the gate contact is inverse to the tapering of the sidewalls of the contact.Type: ApplicationFiled: May 24, 2022Publication date: November 30, 2023Inventors: Oleg Gluschenkov, Yasir Sulehria, Ruilong Xie, Kai Zhao
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Publication number: 20230215800Abstract: A via connection layer for an electronic package and method for fabricating a via connection layer are provided. The via connection layer includes asymmetric via(s) formed in the via connection layer. The asymmetric via include a first sidewall with a first slope angle in a first direction and a second sidewall, where the second sidewall includes a second slope angle in the first direction.Type: ApplicationFiled: December 30, 2021Publication date: July 6, 2023Inventors: Ruilong XIE, Oleg GLUSCHENKOV, Yasir SULEHRIA, Julien FROUGIER, Veeraraghavan S. BASKER
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Publication number: 20230210019Abstract: A Josephson Junction qubit device is provided. The device includes a substrate of silicon material. The device includes first and second electrodes of superconducting metal. The device may include a nanowire created by direct ion implantation on to the silicon material to connect the first and second electrodes. The device may include first and second superconducting regions created by direct ion implantation on to the silicon material, the first superconducting region connecting the first electrode and the second superconducting region connecting the second electrode, with a silicon channel formed by a gap between the first and second superconducting regions.Type: ApplicationFiled: December 28, 2021Publication date: June 29, 2023Inventors: Steven J. Holmes, Devendra K. Sadana, Oleg Gluschenkov, Martin O. Sandberg, Marinus Johannes Petrus Hopstaken, Yasir Sulehria
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Publication number: 20230187510Abstract: Embodiments disclosed herein include a semiconductor structure having a first lower device and a second lower device laterally adjacent to the first lower device at a lower level of the semiconductor structure, a first upper device and a second upper device laterally adjacent to the first upper device at an upper level of the semiconductor structure. The upper level may be vertically above the lower level. The semiconductor structure may also include an angled via electrically connecting the lower device and the first upper device. The angled via may include an angled surface laterally between the first upper device and the second upper device that is angled toward the first upper device relative to a vertical axis.Type: ApplicationFiled: December 15, 2021Publication date: June 15, 2023Inventors: Ruilong Xie, Oleg Gluschenkov, Eric Miller, Yasir Sulehria
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Patent number: 11621297Abstract: A method of forming an electrical device that includes forming an amorphous semiconductor material on a metal surface of a memory device, in which the memory device is vertically stacked atop a first transistor. The amorphous semiconductor material is annealed with a laser anneal having a nanosecond duration to convert the amorphous semiconductor material into a crystalline semiconductor material. A second transistor is formed from the semiconductor material. The second transistor vertically stacked on the memory device.Type: GrantFiled: December 28, 2020Date of Patent: April 4, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alexander Reznicek, Bahman Hekmatshoartabari, Oleg Gluschenkov, Yasir Sulehria
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Patent number: 11309216Abstract: Large grain metal bitlines are formed above magnetic tunnel junction pillars used as MRAM bits without materially affecting the magnetic properties of the magnetic tunnel junctions. A copper or copper alloy bitline having relatively small grains is formed over the pillars. Laser annealing is employed to melt the bitline. Subsequent cooling and recrystallization results in a reduction of the number of grain boundaries in the bitline and a reduction in bitline effective resistivity. Multiple melt/cool cycles may be used. Bitline grains are vertically aligned with the pillars in a resulting structure.Type: GrantFiled: January 27, 2020Date of Patent: April 19, 2022Assignee: International Business Machines CorporationInventors: Alexander Reznicek, Oleg Gluschenkov, Yasir Sulehria, Devika Sil
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Patent number: 11114606Abstract: A harden gap fill dielectric material that has improved chemical and physical properties is formed laterally adjacent to a multilayered magnetic tunnel junction (MTJ) pillar and a top electrode structure of a memory structure. The harden gap fill dielectric material can be formed by introducing, via ion implantation, a bond breaking additive into an as deposited gap fill dielectric material layer and thereafter curing the gap fill dielectric material layer containing the bond breaking additive. The curing includes UV curing alone, or UV curing in combination with laser annealing. The curing employed in the present application does not negatively impact the MTJ pillar or top electrode structure.Type: GrantFiled: September 23, 2019Date of Patent: September 7, 2021Assignee: International Business Machines CorporationInventors: Alexander Reznicek, Devika Sil, Oleg Gluschenkov, Yasir Sulehria
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Publication number: 20210233812Abstract: Large grain metal bitlines are formed above magnetic tunnel junction pillars used as MRAM bits without materially affecting the magnetic properties of the magnetic tunnel junctions. A copper or copper alloy bitline having relatively small grains is formed over the pillars. Laser annealing is employed to melt the bitline. Subsequent cooling and recrystallization results in a reduction of the number of grain boundaries in the bitline and a reduction in bitline effective resistivity. Multiple melt/cool cycles may be used. Bitline grains are vertically aligned with the pillars in a resulting structure.Type: ApplicationFiled: January 27, 2020Publication date: July 29, 2021Inventors: Alexander Reznicek, Oleg Gluschenkov, Yasir Sulehria, Devika Sil
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Publication number: 20210118951Abstract: A method of forming an electrical device that includes forming an amorphous semiconductor material on a metal surface of a memory device, in which the memory device is vertically stacked atop a first transistor. The amorphous semiconductor material is annealed with a laser anneal having a nanosecond duration to convert the amorphous semiconductor material into a crystalline semiconductor material. A second transistor is formed from the semiconductor material. The second transistor vertically stacked on the memory device.Type: ApplicationFiled: December 28, 2020Publication date: April 22, 2021Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Oleg Gluschenkov, Yasir Sulehria
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Publication number: 20210091302Abstract: A harden gap fill dielectric material that has improved chemical and physical properties is formed laterally adjacent to a multilayered magnetic tunnel junction (MTJ) pillar and a top electrode structure of a memory structure. The harden gap fill dielectric material can be formed by introducing, via ion implantation, a bond breaking additive into an as deposited gap fill dielectric material layer and thereafter curing the gap fill dielectric material layer containing the bond breaking additive. The curing includes UV curing alone, or UV curing in combination with laser annealing. The curing employed in the present application does not negatively impact the MTJ pillar or top electrode structure.Type: ApplicationFiled: September 23, 2019Publication date: March 25, 2021Inventors: Alexander Reznicek, Devika Sil, Oleg Gluschenkov, Yasir Sulehria
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Patent number: 10910435Abstract: A method of forming an electrical device that includes forming an amorphous semiconductor material on a metal surface of a memory device, in which the memory device is vertically stacked atop a first transistor. The amorphous semiconductor material is annealed with a laser anneal having a nanosecond duration to convert the amorphous semiconductor material into a crystalline semiconductor material. A second transistor is formed from the semiconductor material. The second transistor vertically stacked on the memory device.Type: GrantFiled: March 27, 2019Date of Patent: February 2, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alexander Reznicek, Bahman Hekmatshoartabari, Oleg Gluschenkov, Yasir Sulehria
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Publication number: 20200388531Abstract: Embodiments of the invention include a method of forming a multi-layer integrated circuit (IC) structure that includes a forming a first IC layer above the substrate, wherein the first IC layer includes a network of interconnect structures, wherein the network of interconnect structures is configured to communicatively couple electronic devices of the IC. A second IC layer is formed over the first IC layer. The second IC layer is implanted with a predetermined ion implantation dose, maintained at a predetermined temperature, and further exposed to electromagnetic radiation from an energy source. The second IC layer is configured to, based at least in part of being exposed to the ion implantation and the electromagnetic radiation, experience changes in the chemical composition of the second IC layer and transform the second IC layer.Type: ApplicationFiled: June 4, 2019Publication date: December 10, 2020Inventors: Devika Sil, Matthew T. Shoudy, Oleg Gluschenkov, Benjamin D. Briggs, Danielle Durrant, Yasir Sulehria
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Publication number: 20200388488Abstract: Embodiments of the invention include a method of forming a multi-layer integrated circuit (IC) structure that includes forming a passive energy source formed from a conductive metal. A dielectric target layer is formed over the first energy source. An active energy source is used to generate electromagnetic radiation having a predetermined wavelength, wherein the dielectric target layer is substantially transparent to the electromagnetic radiation at the predetermined wavelength. The dielectric target layer is exposed to the electromagnetic radiation by transmitting the electromagnetic radiation into and through the dielectric target layer to impact the passive energy source. The passive energy source is configured to, based at least in part on being exposed to the electromagnetic radiation, absorb the electromagnetic radiation, experience a conductive material temperature increase such that the conductive material generates heat energy, and emit the generated heat energy to the dielectric target layer.Type: ApplicationFiled: June 4, 2019Publication date: December 10, 2020Inventors: Devika Sil, Oleg Gluschenkov, Yasir Sulehria, Hosadurga Shobha
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Publication number: 20200312906Abstract: A method of forming an electrical device that includes forming an amorphous semiconductor material on a metal surface of a memory device, in which the memory device is vertically stacked atop a first transistor. The amorphous semiconductor material is annealed with a laser anneal having a nanosecond duration to convert the amorphous semiconductor material into a crystalline semiconductor material. A second transistor is formed from the semiconductor material. The second transistor vertically stacked on the memory device.Type: ApplicationFiled: March 27, 2019Publication date: October 1, 2020Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Oleg Gluschenkov, Yasir Sulehria
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Patent number: 10578981Abstract: Methods for post-lithographic inspection using an e-beam inspection tool of organic extreme ultraviolet sensitive (EUV) sensitive photoresists generally includes conformal deposition of a removable metal carboxide or metal carboxynitride onto the relief image. The conformal deposition of the metal carboxide or metal carboxynitride includes a low temperature vapor deposition process of less than about 100° C. to provide a coating thickness of less than about 5 nanometers. Subsequent to e-beam inspection, the metal carboxide or metal carboxynitride coating is removed using a wet stripping process. Once stripped, the wafer can continue on to further process fabrication without being a sacrificial wafer.Type: GrantFiled: July 25, 2018Date of Patent: March 3, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Luciana Meli Thompson, Ekmini A. De Silva, Yasir Sulehria, Nelson Felix
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Publication number: 20200033733Abstract: Methods for post-lithographic inspection using an e-beam inspection tool of organic extreme ultraviolet sensitive (EUV) sensitive photoresists generally includes conformal deposition of a removable metal carboxide or metal carboxynitride onto the relief image. The conformal deposition of the metal carboxide or metal carboxynitride includes a low temperature vapor deposition process of less than about 100° C. to provide a coating thickness of less than about 5 nanometers. Subsequent to e-beam inspection, the metal carboxide or metal carboxynitride coating is removed using a wet stripping process. Once stripped, the wafer can continue on to further process fabrication without being a sacrificial wafer.Type: ApplicationFiled: July 25, 2018Publication date: January 30, 2020Inventors: Luciana Meli Thompson, Ekmini A. De Silva, Yasir Sulehria, Nelson Felix
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Patent number: 10395925Abstract: A lithographic patterning method includes forming a multi-layer patterning material film stack on a semiconductor substrate. Forming the patterning material film stack includes forming a hard mask layer and forming a resist layer over the hard mask layer. The hard mask layer is formed such that an interface portion of the hard mask layer proximate the resist layer has a higher metal content than other portions of the hard mask layer. The method further includes exposing the patterning material film stack to patterning radiation to form a desired pattern in the resist layer, developing the pattern formed in the resist layer, etching the hard mask layer in accordance with the developed pattern, and removing remaining portions of the resist layer. The hard mask layer illustratively includes metal oxide, metal nitride and/or metal oxynitride, and may exhibit an elevated surface hydrophobicity due to its high metal content interface portion.Type: GrantFiled: December 28, 2017Date of Patent: August 27, 2019Assignee: International Business Machines CorporationInventors: Ekmini Anuja De Silva, Adra Carr, Shanti Pancharatnam, Indira Seshadri, Yasir Sulehria
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Publication number: 20190206681Abstract: A lithographic patterning method includes forming a multi-layer patterning material film stack on a semiconductor substrate. Forming the patterning material film stack includes forming a hard mask layer and forming a resist layer over the hard mask layer. The hard mask layer is formed such that an interface portion of the hard mask layer proximate the resist layer has a higher metal content than other portions of the hard mask layer. The method further includes exposing the patterning material film stack to patterning radiation to form a desired pattern in the resist layer, developing the pattern formed in the resist layer, etching the hard mask layer in accordance with the developed pattern, and removing remaining portions of the resist layer. The hard mask layer illustratively includes metal oxide, metal nitride and/or metal oxynitride, and may exhibit an elevated surface hydrophobicity due to its high metal content interface portion.Type: ApplicationFiled: December 28, 2017Publication date: July 4, 2019Inventors: Ekmini Anuja De Silva, Adra Carr, Shanti Pancharatnam, Indira Seshadri, Yasir Sulehria