Abstract: A memory cell array of an EEPROM is divided into bit columns including 8192 words, each column being a unit for 8-bit access. An input data latch of 8 bits.times.32 words receives 8-bit data when data is written in the memory cell array. When the data is written in the memory cell array, a write controller permits the input data latch to receive the 8-bit data, then refers to an access ID latch to discriminate only the data received within a predetermined time by the input data latch, and writes only the received data into a predetermined divided region of the memory cell array.