Abstract: A light control panel including an image display region including a region corresponding to an image display region in a display panel and a region corresponding to a peripheral circuit region in the display panel is provided between the display panel and a backlight. A pattern image for controlling radiation of light emitted from the backlight to the display panel is displayed in the image display region in the light control panel according to an action state of the peripheral circuit in the display panel.

Abstract: An active matrix substrate includes a first pixel region defined by first and second source bus lines adjacent to each other and first and second gate bus lines adjacent to each other and further includes a first pixel electrode and a first oxide semiconductor TFT that are associated with the first pixel region. The first oxide semiconductor TFT includes an oxide semiconductor layer and a gate electrode electrically connected to the first gate bus line. The oxide semiconductor layer includes a channel region and a low-resistance region including first and second regions located on opposite sides of the channel region. When viewed in a direction normal to the substrate, the low-resistance region extends across the first source bus line to another pixel region and partially overlaps a pixel electrode disposed in the other pixel region with an insulating layer interposed therebetween.

Abstract: A light control panel including an image display region including a region corresponding to an image display region in a display panel and a region corresponding to a peripheral circuit region in the display panel is provided between the display panel and a backlight. A pattern image for controlling radiation of light emitted from the backlight to the display panel is displayed in the image display region in the light control panel according to an action state of the peripheral circuit in the display panel.

Abstract: An active matrix substrate includes a first pixel region defined by first and second source bus lines adjacent to each other and first and second gate bus lines adjacent to each other and further includes a first pixel electrode and a first oxide semiconductor TFT that are associated with the first pixel region. The first oxide semiconductor TFT includes an oxide semiconductor layer and a gate electrode electrically connected to the first gate bus line. The oxide semiconductor layer includes a channel region and a low-resistance region including first and second regions located on opposite sides of the channel region. When viewed in a direction normal to the substrate, the low-resistance region extends across the first source bus line to another pixel region and partially overlaps a pixel electrode disposed in the other pixel region with an insulating layer interposed therebetween.

Abstract: An active matrix substrate includes first and second TFTs. The first TFT includes a first lower electrode, a first insulating layer, a first oxide semiconductor layer, and a first gate electrode. The first oxide semiconductor layer includes a first channel region overlapping the first gate electrode when viewed in a normal direction of the substrate. The first lower electrode has a first light-shielding portion overlapping the entire first channel region and including a first metal film. The second TFT includes a second lower electrode, the first insulating layer, a second oxide semiconductor layer, and a second gate electrode. The second oxide semiconductor layer includes a second channel region overlapping the second gate electrode when viewed in the normal direction. The second lower electrode has a light-transmitting portion overlapping the second channel region and including a first transparent conductive film but not a light-shielding metal film.

Abstract: A gate driver is constituted of a first gate driver including a first shift register that is configured by bistable circuits corresponding to gate bus lines on odd-numbered lines arranged on one side of a display portion, and a second gate driver including a second shift register that is configured by bistable circuits corresponding to gate bus lines on even-numbered lines arranged on another side of the display portion. A first buffer circuit is provided on one end side of each gate bus line, and a second buffer circuit is provided on another end side of each gate bus line. A control signal for controlling the scanning order of the gate bus line is given to the bistable circuit and the second buffer circuit.

Abstract: A gate driver is constituted of a first gate driver including a first shift register that is configured by bistable circuits corresponding to gate bus lines on odd-numbered lines arranged on one side of a display portion, and a second gate driver including a second shift register that is configured by bistable circuits corresponding to gate bus lines on even-numbered lines arranged on another side of the display portion. A first buffer circuit is provided on one end side of each gate bus line, and a second buffer circuit is provided on another end side of each gate bus line. A control signal for controlling the scanning order of the gate bus line is given to the bistable circuit and the second buffer circuit.

Abstract: A gate driver is constituted of a first gate driver including a first shift register that is configured by bistable circuits corresponding to gate bus lines on odd-numbered lines arranged on one side of a display portion and can switch a shift direction, and a second gate driver including a second shift register that is configured by bistable circuits corresponding to gate bus lines on even-numbered lines arranged on another side of the display portion and can switch the shift direction. A first buffer circuit is provided on one side of both ends of each gate bus line, and a second and a third buffer circuits are provided on another side thereof.

Abstract: A gate driver is constituted of a first gate driver including a first shift register that is configured by bistable circuits corresponding to gate bus lines on odd-numbered lines arranged on one side of a display portion and can switch a shift direction, and a second gate driver including a second shift register that is configured by bistable circuits corresponding to gate bus lines on even-numbered lines arranged on another side of the display portion and can switch the shift direction. A first buffer circuit is provided on one side of both ends of each gate bus line, and a second and a third buffer circuits are provided on another side thereof.

Abstract: A unit circuit that constitutes a shift register includes a gate output lowering transistor (T01) whose source terminal is supplied with a second gate low voltage (Vgl2) and a gate output reset transistor (T03) Whose source terminal is supplied with a first gate low voltage (Vgl1), as constituent elements associated with the lowering of gate output. At the time of lowering the gate output, the gate output lowering transistor (T01) is made to be in an on state, and thereafter the gate output reset transistor (T03) is made to be in the on state. In this case, the gate terminal of the gate output reset transistor (T03) is supplied with a scanning signal or a signal having a waveform equivalent to that of the scanning signal outputted from the unit circuit in a subsequent stage.

Abstract: In a display device that adopts an SSD scheme, a demultiplexer circuit has provided for each source bus line, a compensating transistor whose first conduction terminal is connected to the source bus line and whose second conducting terminal is maintained in a floating state. In such a configuration, for example, at the same timing as a connection control transistor changes from an on state to an off state due to a change from a high level to a low level of a control signal that is supplied to a control terminal of the connection control transistor, a control signal that is supplied to a control terminal of the compensating transistor changes from the low level to the high level.

Abstract: In a display device that adopts an SSD scheme, a demultiplexer circuit has provided for each source bus line, a compensating transistor whose first conduction terminal is connected to the source bus line and whose second conducting terminal is maintained in a floating state. In such a configuration, for example, at the same timing as a connection control transistor changes from an on state to an off state due to a change from a high level to a low level of a control signal that is supplied to a control terminal of the connection control transistor, a control signal that is supplied to a control terminal of the compensating transistor changes from the low level to the high level.

Abstract: A demultiplexing circuit provided in a display device including an active matrix substrate includes demultiplexers respectively corresponding to sets of source bus line groups obtained by dividing source bus lines in the active matrix substrate into groups with two or more source bus lines making up one set, and input terminals respectively corresponding to the demultiplexers. Each demultiplexer includes two or more main switching elements respectively corresponding to two or more source bus lines of the corresponding set, and two or more sub-switching elements respectively connected in parallel with the two or more main switching elements, the input terminals are respectively connected to the two or more source bus lines via the two or more main switching elements, and each of the two or more sub-switching elements is controlled to be turned off at a time later than a time when the corresponding main switching element is turned off.

Abstract: To prevent a decrease in display quality caused when a display apparatus performs pause driving. One end of the n-th scanning signal line (GLn) is connected to the n-th stage circuit (UCn) of a driver circuit. The other end of the n-th scanning signal line is connected to a waveform adjusting circuit (HKn) which adjusts the waveform of the pulse signal of the n-th scanning signal line (GLn) by using a clock signal (CKA) and the pulse signal of the m-th scanning signal line (GLn?1) scanned prior to the n-th scanning signal line.

Abstract: In a display device including an active matrix substrate in which a demultiplexing circuit is formed, a boost circuit, which generates a plurality of connection control signals respectively applied to gate terminals of a plurality of connection control transistors as switching elements configuring the demultiplexing circuit are respectively generated, is provided in the demultiplexing circuit. An internal node of each boost circuit is precharged via a transistor turned on by a boosted voltage of an internal node of another boost circuit, and thereafter, a voltage of the internal node of the boost circuit is boosted via a boost capacitor by a control signal applied to a demultiplexing circuit. The boosted voltage of the internal node is applied to a gate terminal of a connection control transistor as a connection control signal.

Abstract: [Object] An object is to suppress an occurrence of display unevenness in a pause-and-drive operation. [Solution] A display device configured to perform pause-and-drive operation includes an nth stage circuit connected to one end of an nth gate bus line, and an nth transistor connected to the other end of the nth gate bus line. One of a first clock signal group (AGCK1 to AGCK6) is input to the nth stage circuit. One of a second clock signal group (BGCK1 to BGCK6) is input to the nth transistor. In a pause period in which all clock signals of the first clock signal group are fixed at an inactive level, one or more pulses (P3 to P6) are included in the second signal group.

Abstract: A gate driver (scanning signal line drive circuit) that can allow a gate output to promptly fall without causing a deterioration in a transistor is implemented. A gate-output fall transistor (T01) and a gate-output stabilization transistor (T02) are provided near an output portion of the unit circuit that constitutes a shift register. A first gate low voltage (Vgl1) having a voltage level that is conventionally used to bring pixel TFTs into an off state is provided to a source terminal of the gate-output stabilization transistor (T02), and a second gate low voltage (Vgl2) having a lower voltage level than the first gate low voltage (Vgl1) is provided to a source terminal of the gate-output fall transistor (T01). Upon allowing the gate output to fall, the gate-output fall transistor (T01) is brought into an on state and then the gate-output stabilization transistor (T02) is brought into an on state.

Abstract: In a display device including an active matrix substrate in which a demultiplexing circuit is formed, a boost circuit, which generates a plurality of connection control signals respectively applied to gate terminals of a plurality of connection control transistors as switching elements configuring the demultiplexing circuit are respectively generated, is provided in the demultiplexing circuit. An internal node of each boost circuit is precharged via a transistor turned on by a boosted voltage of an internal node of another boost circuit, and thereafter, a voltage of the internal node of the boost circuit is boosted via a boost capacitor by a control signal applied to a demultiplexing circuit. The boosted voltage of the internal node is applied to a gate terminal of a connection control transistor as a connection control signal.

Abstract: Each unit circuit that constitutes each of stages of a shift register is provided with a charge supply unit including a third node whose potential becomes high level at identical timing with a first node (a node for holding an electric charge in order to output a scanning signal (output signal) at high level), and capable of supplying an electric charge to the first node throughout a period after the potential of the third node becomes high level until the scanning signal (output signal) at high level is outputted. Here, all of the unit circuits within the shift register have an identical configuration.

Abstract: In each unit circuit constituting a shift register, as thin film transistors configured to lower a gate output, a thin film transistor whose state is controlled by a first reset signal and a thin film transistor whose state is controlled by a second reset signal are provided. Then, during the period in which a thin film transistor functioning as a buffer transistor is maintained in an ON state, the first reset signal changes from a low level to a high level, and then the second reset signal changes from a low level to a high level at a timing at which a corresponding gate bus line is to be changed from a selected state to an unselected state.