Abstract: An image processing apparatus reads image data written in a video memory, performs an expansion or reduction process of the image data by filter computation, and sequentially outputs the image data to a display device in synchronization with a display clock. In the image processing apparatus, a primary buffer stores the image data read from the video memory. A first computing unit performs a first filter computation of the image data read from the primary buffer in synchronization with the display clock. A secondary buffer stores the image data outputted from the first computing unit. A second computing unit performs a second filter computation of the image data outputted from the secondary buffer in synchronization with the display clock, so that the image data is expanded or reduced in real time basis by a sequence of the first filter computation and the second filter computation.

Abstract: An image processing apparatus is designed for displaying an image written in a video memory, on a display device in the form of an array of dots, by performing distortion correction of the image based on a distortion rate, and by performing tilt correction of the image based on a tilt angle. In the image processing apparatus, a first computing part computes a position before the tilt correction based on the tilt angle, for each dot of the image displayed in the display device. A second computing part computes a position before the distortion correction based on the distortion rate, for each position computed by the first computing part. A color data computing part computes color data of the position computed by the second computing part, based on color data of dots around the position in the video memory.

Abstract: In a music reproducing apparatus, a timbre data memory has a limited capacity for storing timbre data corresponding to a first number of timbres, which is less than a second number of timbres reserved in a data source. An interface can be operated to transfer the timbre data from the data source to the timbre data memory so that the timbre data memory stores the transferred timbre data. A score data memory stores score data representing a music piece. A tone generator is set with a tone generating parameter derived from the score data stored in the score data memory for generating tones of the music piece. A performance controller interprets the score data to read out timbre data designated by the score data from the timbre data memory for setting the tone generator with the read timbre data so that the tone generator can generate the tones having timbres specified by the score data.

Abstract: A method and a data transfer apparatus capable of handling DMA block transfer interruptions are provided. The data transfer apparatus includes a plurality of direct memory access (DMA) channels each having different priorities and at least one backup channel information memory for saving control information necessary for a restart of an interrupted DMA transfer through one of the DMA channels. The data transfer apparatus further includes a control means responsive to transfer commands which command DMA transfers through the DMA channels. In addition, the control means executes various interrupt handling steps when a transfer command interrupts an execution of a DMA transfer through one of the DMA channels having a lower priority than the priority of the DMA channel used by the interrupting transfer command, so that an interruption of an important data transfer can be prevented.

Abstract: A data processing apparatus includes an instruction issuing unit, an interval holding unit, a passing control unit, and a nullification processing unit. The instruction issuing unit tentatively issues a vector store instruction having no definitive data as an instruction not subjected to actual vector store processing. The interval holding unit obtains and holds a store interval block address to be operated by the vector store instruction tentatively issued from the instruction issuing unit. The passing control unit compares a block address indicated by a scalar load/store instruction issued from the instruction issuing unit with the store interval block address held by the interval holding unit. If the block address falls within the range of the store interval block addresses, the passing control unit causes processing for the scalar load/store instruction to wait until the vector store instruction is finally issued from the instruction issuing unit and processed.

Abstract: In a buffer memory device intermediate between a data processing unit and a main memory to memorize and read out an operand data block and an instruction data block in response to an operand request and an instruction request, respectively, the operand and the instruction data blocks have an operand block size and an instruction block size equal to N times the operand block size, respectively, where N is an integer greater than unity. The number N is preferably equal to 2.sup.n, where n is a natural number. The buffer memory device comprises a data buffer having a plurality of cache areas each of which has a predetermined area size equal to the operand block size. Thus, the operand data block occupies a single one of the cache areas while the instruction data block occupies a plurality of the cache areas, N in number. The operand data blocks coexist with the instruction data blocks in the data buffer at different block sizes.