Abstract: A design method of a bus interface that includes an I/F interposed between chips, includes determining a bus width of the bus interface between chips and a type of the bus interface, based on a physical constraint condition between the chips, and automatically generating a bus IP core that comprises a circuit configured in accordance with the determined bus width and the bus interface.

Abstract: In a layout system of a logic circuit, a buffer inserted into a critical path is arranged/wired in an arranged region of a circuit block of a primitive layout in such a manner that delay time of the critical path in the primitive layout can be limited to an allowable value. The layout system is comprised of unarranged region information extracting means for extracting a position and a size of an unarranged region from layout data after an arranging/wiring process; virtual node inserting means for inserting a virtual node into a wiring segment located adjacent to the unarranged region, the virtual node constituting a connection point between the wiring segment and the unarranged region; wiring parameter extracting means for extracting a wiring parameter constructed of a wiring resistance and a wiring capacitance of the wiring segment; and path delay time calculating means for calculating delay time of a path based upon the wiring parameter and a delay parameter specific to an element.

Abstract: A microprocessor which is constructed to output outside a pipeline flash signal in response to a branch caused by a conditional branch instruction being to be taken, includes a decoder unit decoding and producing decoded information of each of instructions to be executed, the decoder unit further producing branch conduction information designated by the conditional branch instruction, a latch latching the decoded information in response to a write-enable signal and outputting it in response to a read-enable signal, an execution unit performing a data processing operation in response to the decoded information from the latch and including a status word register for temporarily storing an execution state thereof, and a branch detection unit for detecting whether or not a branch is to be taken in response to the branch condition information and the execution state and responding to the write-enable signal to produce a detection signal when the branch is detected to be taken, the pipeline flash signal being there

Abstract: A microprocessor includes a plurality of registers connected to a plurality of buses. Selectors each select one of output signals of the registers to output the selected one of the output signals to one of the buses. The number of the register output signal lines connected to the buses is reduced to reduce a load capacity of the buses and to reduce an occupancy area of register output circuits and a consumption power.