Patents by Inventor Yasufumi Morimoto
Yasufumi Morimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11169011Abstract: A fluid measuring apparatus, including a pair of ultrasonic wave probes in which one is disposed more upstream than the other, a processor, and a non-transitory storage medium containing program instructions therein. The execution of the program instructions by the processor causes the fluid measuring apparatus to provide functions of a period measuring unit that measures a first propagation period during which ultrasonic wave propagates from the one ultrasonic wave probe to the other, and a second propagation period during which ultrasonic wave propagates from the other ultrasonic wave probe to the one ultrasonic wave probe, and a flow velocity measuring unit that derives a flow velocity of the fluid by cancelling errors in a first flow velocity that is derived by measuring the second propagation period after measuring the first propagation period, and a second flow velocity that is derived by measuring the first propagation period after measuring the second propagation period.Type: GrantFiled: May 1, 2018Date of Patent: November 9, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventors: Masami Kishiro, Yasufumi Morimoto
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Patent number: 10134869Abstract: To provide a semiconductor device having improved reliability. After formation of an n+ type semiconductor region for source/drain, a first insulating film is formed on a semiconductor substrate so as to cover a gate electrode and a sidewall spacer. After heat treatment, a second insulating film is formed on the first insulating film and a resist pattern is formed on the second insulating film. Then, these insulating films are etched with the resist pattern as an etching mask. The resist pattern is removed, followed by wet washing treatment. A metal silicide layer is then formed by the salicide process.Type: GrantFiled: December 4, 2016Date of Patent: November 20, 2018Assignee: Renesas Electronics CorporationInventors: Yasufumi Morimoto, Kiyonobu Takahashi, Morihiko Kume
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Publication number: 20180245960Abstract: A fluid measuring apparatus, including a pair of ultrasonic wave probes in which one is disposed more upstream than the other, a processor, and a non-transitory storage medium containing program instructions therein. The execution of the program instructions by the processor causes the fluid measuring apparatus to provide functions of a period measuring unit that measures a first propagation period during which ultrasonic wave propagates from the one ultrasonic wave probe to the other, and a second propagation period during which ultrasonic wave propagates from the other ultrasonic wave probe to the one ultrasonic wave probe, and a flow velocity measuring unit that derives a flow velocity of the fluid by cancelling errors in a first flow velocity that is derived by measuring the second propagation period after measuring the first propagation period, and a second flow velocity that is derived by measuring the first propagation period after measuring the second propagation period.Type: ApplicationFiled: May 1, 2018Publication date: August 30, 2018Applicant: FUJI ELECTRIC CO., LTD.Inventors: Masami KISHIRO, Yasufumi MORIMOTO
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Publication number: 20170186850Abstract: To provide a semiconductor device having improved reliability. After formation of an n+ type semiconductor region for source/drain, a first insulating film is formed on a semiconductor substrate so as to cover a gate electrode and a sidewall spacer. After heat treatment, a second insulating film is formed on the first insulating film and a resist pattern is formed on the second insulating film. Then, these insulating films are etched with the resist pattern as an etching mask. The resist pattern is removed, followed by wet washing treatment. A metal silicide layer is then formed by the salicide process.Type: ApplicationFiled: December 4, 2016Publication date: June 29, 2017Inventors: Yasufumi MORIMOTO, Kiyonobu TAKAHASHI, Morihiko KUME
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Patent number: 9117849Abstract: A method and apparatus of forming a nonvolatile semiconductor device including forming a first gate insulating film on a main surface of a first semiconductor region, forming a first gate electrode on the first gate insulating film, forming a second gate insulating film, forming a second gate electrode over a first side surface of the first gate electrode, selectively removing the second gate insulating film, etching the second gate insulating film kept between the second gate electrode and a main surface of the first semiconductor region in order to form an etched charge storage layer, introducing first impurities in the first semiconductor region in a self-aligned manner to the second gate electrode in order to form a second semiconductor region, annealing the semiconductor substrate to extend the second semiconductor region to an area under the second gate electrode.Type: GrantFiled: July 8, 2014Date of Patent: August 25, 2015Assignee: Renesas Electronics CorporationInventors: Kenichi Akita, Daisuke Okada, Keisuke Kuwahara, Yasufumi Morimoto, Yasuhiro Shimamoto, Kan Yasui, Tsuyoshi Arigane, Tetsuya Ishimaru
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Publication number: 20150008507Abstract: Provided are a semiconductor device in which a data re-write operation can be performed a larger number of times and a data re-write operation is performed at a higher speed and a manufacturing method thereof. The semiconductor device includes a substrate, a first gate electrode, a second gate electrode, an insulating film, and a pair of source/drain regions. The first gate electrode is formed of a semiconductor layer containing an impurity of a first conductivity type. The second gate electrode is formed of a semiconductor layer containing an impurity of a second conductivity type. Each of the source/drain regions contains an impurity of the first conductivity type. The source region includes a first source region and a second source region having a concentration of the impurity of the first conductivity type higher than that of the first source region.Type: ApplicationFiled: July 1, 2014Publication date: January 8, 2015Inventor: Yasufumi MORIMOTO
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Publication number: 20140322874Abstract: A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.Type: ApplicationFiled: July 8, 2014Publication date: October 30, 2014Inventors: Kenichi Akita, Daisuke Okada, Keisuke Kuwahara, Yasufumi Morimoto, Yasuhiro Shimamoto, Kan Yasui, Tsuyoshi Arigane, Tetsuya Ishimaru
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Publication number: 20130140622Abstract: A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.Type: ApplicationFiled: January 31, 2013Publication date: June 6, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Kenichi Akita, Daisuke Okada, Keisuke Kuwahara, Yasufumi Morimoto, Yasuhiro Shimamoto, Kan Yasui, Tsuyoshi Arigane, Tetsuya Ishimaru
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Patent number: 8390053Abstract: A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.Type: GrantFiled: August 8, 2008Date of Patent: March 5, 2013Assignee: Renesas Electronics CorporationInventors: Kenichi Akita, Daisuke Okada, Keisuke Kuwahara, Yasufumi Morimoto, Yasuhiro Shimamoto, Kan Yasui, Tsuyoshi Arigane, Tetsuya Ishimaru
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Publication number: 20110001179Abstract: In a non-volatile memory in which charge is injected from a gate electrode to a charge accumulating layer, charge injection efficiency, charge retention characteristic and reliability are all improved compared with a conventional gate structure. In a nonvolatile memory which carries out write/erasure by changing the total charge amount by injecting electrons and holes into a silicon nitride film which makes up a charge accumulating layer, in order to highly efficiently carry out charge injection from a gate electrode, the gate electrode of a memory cell is made up of a two-layer film of a non-doped polysilicon layer and a metal material electrode layer.Type: ApplicationFiled: June 22, 2010Publication date: January 6, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Itaru YANAGI, Digh HISAMOTO, Daisuke OKADA, Atushi YOSHITOMI, Yasufumi MORIMOTO, Toshiyuki MINE
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Publication number: 20100207192Abstract: A non-volatile semiconductor memory device capable of more efficiently trapping charges in a charge storage layer without increasing the thickness of the charge storage layer, as well as a manufacturing method thereof. In the non-volatile semiconductor memory device a tunnel insulating film, a charge storage layer, a block insulating film, and a gate electrode are disposed successively between a first source/drain region and a second source/drain region above a semiconductor substrate. The charge storage layer has a first layer and second layers, the first layer has a first nitrogen atom concentration, each of the second layers has a second nitrogen atom concentration, higher than the first nitrogen atom concentration and faces one of the tunnel insulating film and the block insulator.Type: ApplicationFiled: February 2, 2010Publication date: August 19, 2010Inventors: Toshiya UENISHI, Yasufumi Morimoto
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Publication number: 20090050955Abstract: A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.Type: ApplicationFiled: August 8, 2008Publication date: February 26, 2009Inventors: Kenichi AKITA, Daisuke OKADA, Keisuke KUWAHARA, Yasufumi MORIMOTO, Yasuhiro SHIMAMOTO, Kan YASUI, Tsuyoshi ARIGANE, Tetsuya ISHIMARU
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Patent number: 6914011Abstract: A film deposition system comprises a chamber having an internal space, a support part provided in the internal space of the chamber for supporting a substrate, a gas supply part supplying gas to the internal space and a heating part heating the substrate. After an oxide film is formed on the substrate, the gas supply part supplies oxygen or a gas mixture of oxygen and ozone to the internal space while the heating part heats the substrate. Thus provided is a film deposition system capable of flattening an oxide film.Type: GrantFiled: August 14, 2003Date of Patent: July 5, 2005Assignee: Renesas Technology Corp.Inventors: Yoshio Hayashide, Kazuo Kobayashi, Yasufumi Morimoto
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Publication number: 20040163599Abstract: A film deposition system comprises a chamber having an internal space, a support part provided in the internal space of the chamber for supporting a substrate, a gas supply part supplying gas to the internal space and a heating part heating the substrate. After an oxide film is formed on the substrate, the gas supply part supplies oxygen or a gas mixture of oxygen and ozone to the internal space while the heating part heats the substrate. Thus provided is a film deposition system capable of flattening an oxide film.Type: ApplicationFiled: August 14, 2003Publication date: August 26, 2004Applicant: RENESAS TECHNOLOGY CORP.Inventors: Yoshio Hayashide, Kazuo Kobayashi, Yasufumi Morimoto
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Publication number: 20030129549Abstract: A direct positive silver halide photographic light-sensitive material is used for forming a light-absorbing layer of a lenticular lens sheet that includes a film-form substrate and a plurality of light input lenses provided on a light input side of the substrate, the light absorbing layer (black stripes) being provided on a light output side of the substrate in a region other than a condensing region of each of the light input lenses, the silver halide photographic light-sensitive material including a support, and at least one light-sensitive layer having light-sensitive silver halide grains with a grain size of 1 &mgr;m or less at a silver coat weight of 1.5 g/m2 or more on one side of the support, wherein on the side of the support opposite the light-sensitive layer there is no light absorbing layer, and by developing after exposing, from the side opposite the light-sensitive layer via the light input lenses, the light absorbing layer is formed based on a silver image.Type: ApplicationFiled: November 14, 2002Publication date: July 10, 2003Inventors: Junji Miyata, Kenichi Yasuda, Yasufumi Morimoto, Kumpei Oda, Masashi Nishiyama
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Patent number: 6442704Abstract: A ring oscillator clock frequency measuring circuit includes a reference clock count timer and a ring oscillator clock count timer. The reference clock count timer starts its counting of a reference clock signal in response to a start instruction fed from a CPU, and outputs an overflow signal when its counting reaches a preset value. The ring oscillator clock count timer starts its counting of pulses of a ring oscillator clock signal in response to the start instruction fed from the CPU, and continues its counting until the reference clock count timer generates the overflow signal. The frequency of the ring oscillator clock signal is obtained from the count value of the ring oscillator clock count timer. This makes it possible to measure the frequency of the ring oscillator clock signal at high accuracy, and to reduce the current consumption by operating the CPU based on the ring oscillator clock signal after the measurement.Type: GrantFiled: November 16, 1999Date of Patent: August 27, 2002Assignees: Mitsubishi Electric System LSI Design Corporation, Mitsubishi Denki Kabushiki KaishaInventors: Yasufumi Morimoto, Takeshi Fujii
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Patent number: 5185240Abstract: Disclosed is an autopositive silver halide photographic material which comprises at least one silver halide emulsion layer, characterized in that said emulsion layer or at least one other hydrophilic colloid layers contains at least one compound selected from the group consisting of compounds represented by the following general formulas (1), (2) and (3): ##STR1## wherein R.sub.1 represents hydrogen atom or an alkyl group; and R.sub.2, R.sub.3 and R.sub.4 each represents hydrogen atom, a halogen atom, an alkyl group or an alkoxy group; ##STR2## wherein R.sub.5 represents hydrogen atom or an alkyl group; and R.sub.6 and R.sub.7 each represents hydrogen atom, an alkyl group, a halogen atom or an aryl group; ##STR3## wherein R.sub.8 represents a lower alkylene group; X represents a halogen atom, nitro group, hydroxy group, a cyano group, a lower alkyl group, a lower alkoxy group, ##STR4## or --SO.sub.3 M; R.sub.12 represents hydrogen atom, --OM, a lower alkyl group, a lower alkoxy group or ##STR5## R.sub.Type: GrantFiled: August 10, 1990Date of Patent: February 9, 1993Assignee: Fuji Photo Film Co., Ltd.Inventors: Junji Miyata, Satoshi Kanetake, Yasufumi Morimoto, Kenji Hanayama