Patents by Inventor Yasuharu Ichinose
Yasuharu Ichinose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9331063Abstract: A semiconductor device simplifies the manufacturing process. The device includes a protective chip which has a surface Zener diode to protect a light emitting chip with an LED formed therein from surge voltage. The protective chip is mounted over a wiring electrically coupled through a metal wire to an anode electrode coupled to a p-type semiconductor region whose conductivity type is the same as that of the semiconductor substrate of the chip. The anode electrode of the protective chip is electrically coupled to the back surface of the chip without PN junction, so even if the back surface is in contact with the wiring, no problem occurs with the electrical characteristics of the Zener diode. This eliminates the need to form an insulating film on the back surface of the chip to prevent contact between the back surface and the wiring, thus simplifying the manufacturing process.Type: GrantFiled: May 18, 2015Date of Patent: May 3, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Ryo Niide, Shinichi Yamada, Yasuharu Ichinose, Toshiya Nozawa
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Publication number: 20150249077Abstract: A semiconductor device simplifies the manufacturing process. The device includes a protective chip which has a surface Zener diode to protect a light emitting chip with an LED formed therein from surge voltage. The protective chip is mounted over a wiring electrically coupled through a metal wire to an anode electrode coupled to a p-type semiconductor region whose conductivity type is the same as that of the semiconductor substrate of the chip. The anode electrode of the protective chip is electrically coupled to the back surface of the chip without PN junction, so even if the back surface is in contact with the wiring, no problem occurs with the electrical characteristics of the Zener diode. This eliminates the need to form an insulating film on the back surface of the chip to prevent contact between the back surface and the wiring, thus simplifying the manufacturing process.Type: ApplicationFiled: May 18, 2015Publication date: September 3, 2015Inventors: Ryo NIIDE, Shinichi YAMADA, Yasuharu ICHINOSE, Toshiya NOZAWA
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Patent number: 9070614Abstract: A semiconductor device simplifies the manufacturing process. The device includes a protective chip which has a surface Zener diode to protect a light emitting chip with an LED formed therein from surge voltage. The protective chip is mounted over a wiring electrically coupled through a metal wire to an anode electrode coupled to a p-type semiconductor region whose conductivity type is the same as that of the semiconductor substrate of the chip. The anode electrode of the protective chip is electrically coupled to the back surface of the chip without PN junction, so even if the back surface is in contact with the wiring, no problem occurs with the electrical characteristics of the Zener diode. This eliminates the need to form an insulating film on the back surface of the chip to prevent contact between the back surface and the wiring, thus simplifying the manufacturing process.Type: GrantFiled: May 23, 2013Date of Patent: June 30, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Ryo Niide, Shinichi Yamada, Yasuharu Ichinose, Toshiya Nozawa
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Publication number: 20130334562Abstract: A semiconductor device simplifies the manufacturing process. The device includes a protective chip which has a surface Zener diode to protect a light emitting chip with an LED formed therein from surge voltage. The protective chip is mounted over a wiring electrically coupled through a metal wire to an anode electrode coupled to a p-type semiconductor region whose conductivity type is the same as that of the semiconductor substrate of the chip. The anode electrode of the protective chip is electrically coupled to the back surface of the chip without PN junction, so even if the back surface is in contact with the wiring, no problem occurs with the electrical characteristics of the Zener diode. This eliminates the need to form an insulating film on the back surface of the chip to prevent contact between the back surface and the wiring, thus simplifying the manufacturing process.Type: ApplicationFiled: May 23, 2013Publication date: December 19, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Ryo NIIDE, Shinichi YAMADA, Yasuharu ICHINOSE, Toshiya NOZAWA
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Publication number: 20060079027Abstract: A manufacturing method of a thin and small-sized semiconductor device, which is integrated into an electronic instrument. A silicon wafer is prepared, and oxide films are formed on the main face and the rear face of the wafer. An insulating film is selectively formed on the main face of the wafer to make through holes. Metal-laminated films are formed on the oxide films on the bottoms of the through holes, and further first and second metal films are formed on the metal-laminated films to form metal pedestals. Next, a semiconductor chip wherein a diode is formed is fixed onto the main face of one of the metal pedestals through one electrode of the chips, and the other electrode is connected to the other of the metal pedestals through an electroconductive wire. Next, the semiconductor chip, the wire and so on are covered with an insulating resin layer, and then the silicon wafer and the oxide film are removed so that the oxide film stuck onto the rear face of the sealant remains.Type: ApplicationFiled: May 16, 2003Publication date: April 13, 2006Applicant: Renesas Technology CorporationInventors: Kohei Yamada, Yasuharu Ichinose, Hiroyuki Nagase
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Patent number: 7023027Abstract: A small semiconductor package having two electrodes, which can be produced at reduced cost and which features high reliability. The package has a structure in which an anode and a cathode are arranged on one surface of a semiconductor chip, each electrode having a bump electrode for connecting the electrode to an external substrate. An insulating resin is provided on the surface of the semiconductor chip and on the surfaces of the bump electrodes, except at least for the connection portions to the external substrate.Type: GrantFiled: November 15, 2002Date of Patent: April 4, 2006Assignee: Renesas Technology Corp.Inventors: Toshiya Teramae, Junichi Saeki, Yasuharu Ichinose, Shuichi Suzuki
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Publication number: 20050009298Abstract: For marking a package efficiently at low cost, there is provided a dicing sheet 25 having transfer patterns 28A, 28B and an alignment mark 31 disposed at predetermined positions on a main surface of a base material 26, and an orientation flat 32 of a semiconductor wafer 1 and the alignment mark 31 are aligned with each other, then the main surface of the dicing sheet with the transfer patterns 28A, 28B and the alignment mark 31 disposed thereon and a back surface of the semiconductor wafer 1 are affixed to each other, and thereafter heat and pressure are applied to a back surface of the dicing sheet 25, thereby allowing the transfer patterns 28A and 28B to be transferred at a time to back surfaces of semiconductor chips from the dicing sheet 25.Type: ApplicationFiled: September 20, 2001Publication date: January 13, 2005Inventors: Shuichi Suzuki, Hiroyuki Nagase, Yasuharu Ichinose, Teruhiro Mitsuyasu
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Patent number: 6605854Abstract: The package size of a diode is made smaller. On the element forming face of a semiconductor substrate having a p−-type conductive type, after a hyper-abrupt p+n+ junction of a p+-type diffusion layer, an n+-type hyper-abrupt layer, an n−-epitaxial layer, an n-type low resistance layer and an n+-type diffusion layer is formed, an anode electrode is formed on the top of the p+-type diffusion layer and a cathode electrode is formed on the top of the n+-type diffusion layer. Thereafter, electrode bumps are formed on the top of the anode electrode and the cathode electrode to thereby manufacture a small diode that can be facedown bonded onto a mounting board.Type: GrantFiled: January 17, 2002Date of Patent: August 12, 2003Assignee: Hitachi, Ltd.Inventors: Hiroyuki Nagase, Shuichi Suzuki, Masaki Otoguro, Yasuharu Ichinose, Teruhiro Mitsuyasu
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Publication number: 20030094621Abstract: A small semiconductor package having two electrodes suppressing the cost and featuring high reliability. The package has a structure in which an anode and a cathode are arranged on one surface of a semiconductor chip, each electrode having a bump electrode for connecting the electrode to an external substrate. An insulating resin is provided on the surface of the semiconductor chip and on the surfaces of the bump electrodes except at least the connection portions to the external substrate.Type: ApplicationFiled: November 15, 2002Publication date: May 22, 2003Inventors: Toshiya Teramae, Junichi Saeki, Yasuharu Ichinose, Shuichi Suzuki
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Publication number: 20020102804Abstract: The package size of a diode is made smaller. On the element forming face of a semiconductor substrate having a p−-type conductive type, after a hyper-abrupt p+n+ junction of a p+-type diffusion layer, an n+-type hyper-abrupt layer, an n−-epitaxial layer, an n-type low resistance layer and an n+-type diffusion layer is formed, an anode electrode is formed on the top of the p+-type diffusion layer and a cathode electrode is formed on the top of the n+-type diffusion layer. Thereafter, electrode bumps are formed on the top of the anode electrode and the cathode electrode to thereby manufacture a small diode that can be facedown bonded onto a mounting board.Type: ApplicationFiled: January 17, 2002Publication date: August 1, 2002Applicant: Hitachi, Ltd.Inventors: Hiroyuki Nagase, Shuichi Suzuki, Masaki Otoguro, Yasuharu Ichinose, Teruhiro Mitsuyasu