Abstract: A semiconductor integrated circuit device includes a DLL circuit. The DLL circuit includes a frequency divider which frequency-divides an input clock at a frequency dividing ratio which is varied depending on a frequency of the input clock and thus results in a dummy clock and a reference clock. A delay system includes a variable delay circuit which delays the dummy clock. A control circuit controls a delay amount of the variable delay circuit so that a phase of a delayed dummy clock from the delay system and the reference clock becomes zero.

Abstract: A semiconductor memory has pairs of bit lines connected to its memory cells. Sense amps are connected across the bit line pairs. Column gate pairs are connected to the bit line pairs, and data bus pairs are connected to the bit line pairs via the column gate pairs. A column gate drive control circuit is connected to the column gate pairs and turns selected column gate pairs off during a write mask operation.

Abstract: The present invention is an FCRAM comprising a first stage for performing command decoding, a second stage for performing sense amplifier activation, and a third stage for performing data input and output, configured in a pipeline structure, a plurality of data bits being transferred in parallel between the sense amplifiers and the third stage, wherein sense amplifiers are deactivated automatically and a reset operation is performed after data has been transferred in parallel between sense amplifiers and the third stage, in response to a standard read or write command.

Abstract: The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.

Abstract: There is provided a semiconductor integrated circuit memory comprising banks each having at least one memory cell array and connected to a first data bus. Each of the banks includes a control part which is supplied with information indicated by a command and thus controls a data write or read operation on a corresponding bank. The control part controls data write and read operations on the corresponding bank so that the corresponding bank is prevented from occupying the first data bus until read data is output to the first data bus by the data read operation.

Abstract: A semiconductor system includes at least one logic chip and at least one memory chip arranged such that one side of the at least one memory chip faces one side of the at least one logic chip. The semiconductor system further includes first input/output nodes, provided for the at least one logic chip, for data transfer with an adjacent memory chip, second input/output nodes, provided for the at least one memory chip, for data transfer with an adjacent logic chip, and a package housing the at least one logic chip and the at least one memory chip, wherein the first input/output nodes are arranged along the one side of the at least one logic chip, and the second input/output nodes are arranged along the one side of the at least one memory chip.

Abstract: A semiconductor device includes a variable-delay circuit which delays an input-clock signal to generate a delay clock signal, a clock-control circuit which selects one of the input-clock signal and the delayed clock signal, an output circuit which outputs data in synchronism with a clock signal selected by the clock-control circuit, and a DLL circuit which adjusts a delay of the variable-delay circuit. The DLL circuit includes a delay-control circuit which adjusts the delay of the variable-delay circuit, and a clock-selection circuit which controls the clock-control circuit to select one of the input-clock signal and the delayed clock signal. The variable-delay circuit is controlled such that the delay is not increased when the input-clock signal is selected by the clock-selection circuit.

Abstract: Switching transistors 20, 22, 22P, 21, 23 and 23P and a portion of control circuit for transistors 20 and 21 constitutes a bit line reset circuit on memory cell side. In reading `H` from the memory cell connected to a bit line BLC or *BLC, the both bit lines are set at a higher reset potential Vii, while in reading `L`, the both bit lines are reset at a lower reset potential Vss. Transfer gates 10 and 11 are turned off before sufficient amplification of a potential difference between the bit lines BL and *BL. The operation of restoring into a memory cell read destructively from is performed in parallel with the operation of bit line reset.

Abstract: A muffler for a two-stroke internal combustion engine includes an expansion chamber into which exhaust gas ejected from the exhaust port of the engine is introduced. An air-supplying device is adapted to supply outside air to the expansion chamber. The air-supplying device is actuated by taking advantage of the pressure pulsation in the crank case of the engine, and is constituted by a diaphragm pump.

Abstract: In a semiconductor memory device operable in synchronism with a clock signal externally supplied thereto, there are provided a first part which detects a state of a predetermined signal after a given command is input to the semiconductor memory; and a second part which sets, on the basis of the state of the predetermined signal, the semiconductor memory device to a self-refresh mode in which a refresh operation is carried out without an external signal.

Abstract: In a two-stroke internal combustion engine, output power is increased and total hydrocarbon (THC) exhaust is decreased as a result of small structural changes. An exhaust port and scavenging ports are configured and disposed such that they are open in a reduced period of the combustion cycle.

Abstract: In a two-stroke internal combustion engine, total hydrocarbon (THC) exhaust is decreased as a result of small structural changes and without loss of output power. A Schnurle scavenging-type combustion chamber has a hemispherical main surface and an annular skirt-like squish band, and a spark plug is disposed for a spark point to be substantially at the center of the combustion chamber. The squish band has minimized width.

Abstract: A muffler for a two-stroke internal combustion engine has an expansion chamber into which a rush of exhaust gas is introduced from the engine. In the vicinity of an exhaust gas inlet from the engine into the expansion chamber, the muffler has an external air intake for external air to be suctionally introduced into the expansion chamber by the rush of exhaust gas. With the external air introduced, carbon monoxide (CO) emission into the ambient is reduced.

Abstract: A muffler structure for an internal combustion engine is disclosed which is capable of diminishing occurrence of fraying and lowering of exhaust gas cleaning performance and durability, and which enables replacement of the catalytic cloth and the like to readily be carried out. The muffler structure for an internal combustion engine comprises a muffler 10 and a catalytic assembly 30 disposed in the muffler 10, the catalytic assembly 30 including a spark arresting wire mesh 32 and a catalytic cloth 37 fitted over the spark arresting wire mesh 32, the catalytic cloth 37 has its peripheral edge 37a covered entirely or in substantial part and retained with side walls 34, 34, 36 peripherally provided on the spark arresting wire mesh 32.

Abstract: An exhaust muffler structure of an internal combustion engine in which a catalyzer is readily and easily mounted and removed to carry out the assembling work of the muffler and the maintenance work such as cleaning and replacing the parts of the muffler with ease; the generation of vibration and noise are to be prevented; and the purification capacity and durability of the catalyzer are to be improved. The exhaust muffler structure comprising: an exhaust muffler having inner and outer exhaust muffler halves which are detachably combined with each other; a communication hole formed on the exhaust muffler for guiding exhaust gas from an internal combustion engine to the exhaust muffler; a cylindrical member having a catalyzer between resilient supporting nets, characterized in that the cylindrical member is disposed in a space in the exhaust muffler with a body of the cylindrical member being supported between the both inner and outer exhaust muffler halves.

Abstract: An adiabatic intake insulator inserted into a portion for connecting a carburetor to a small two-cycle gasoline engine or the like in which the generation of cracks due to stress concentration when bolts are fastened are restrained and the looseness of the fastening member due to the shortage of fastening torque is prevented. The intake insulator comprises: portions for supporting and securing a carburetor; an intake passage through which air-fuel mixture from the carburetor is introduced to the engine; portions for securing the intake insulator to the engine each comprising a through hole for a bolt and a counterbore for accommodating a head of the bolt; and a channel formed on a circumference of a bottom of the counterbore.

Abstract: A structure for protecting connection terminals of a battery pack and connection terminals of an electronic apparatus to be loaded with the battery pack. The electronic apparatus and battery pack each has a terminal portion including a cover for protection. When the battery pack is removed from the apparatus, the cover of the former and the cover of the latter conceal and protect their associated connection terminals from accidents.

Abstract: The present invention relates to a two-cycle internal combustion gasoline engine cylinder. The two-cycle engine cylinder according to this invention is characterized in that a smooth hard chromium plated layer is formed on a combustion chamber top inner surface of the cylinder.