Patents by Inventor Yasuhide Yakushi

Yasuhide Yakushi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11280024
    Abstract: The present invention suppresses anomalous growth of a Group III nitride semiconductor at the periphery of a seed substrate. The invention is directed to a method for producing a Group III nitride semiconductor including feeding a nitrogen-containing gas into a molten mixture of a Group III metal and a flux placed in a furnace, to thereby grow a Group III nitride semiconductor on a seed substrate. The oxygen concentration of the furnace internal atmosphere is elevated after the growth initiation temperature of the Group III nitride semiconductor has been achieved. In a period from the initiation of the growth to a certain timing, the oxygen concentration of the furnace internal atmosphere is controlled to 0.02 ppm or less, and thereafter, to greater than 0.02 ppm and 0.1 ppm or less.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: March 22, 2022
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Takayuki Sato, Miki Moriyama, Shiro Yamazaki, Yasuhide Yakushi
  • Publication number: 20200299857
    Abstract: The present invention suppresses anomalous growth of a Group III nitride semiconductor at the periphery of a seed substrate. The invention is directed to a method for producing a Group III nitride semiconductor including feeding a nitrogen-containing gas into a molten mixture of a Group III metal and a flux placed in a furnace, to thereby grow a Group III nitride semiconductor on a seed substrate. The oxygen concentration of the furnace internal atmosphere is elevated after the growth initiation temperature of the Group III nitride semiconductor has been achieved. In a period from the initiation of the growth to a certain timing, the oxygen concentration of the furnace internal atmosphere is controlled to 0.02 ppm or less, and thereafter, to greater than 0.02 ppm and 0.1 ppm or less.
    Type: Application
    Filed: March 10, 2020
    Publication date: September 24, 2020
    Inventors: Takayuki SATO, Miki MORIYAMA, Masateru YAMAZAKI, Taku FUJIMORI, Shiro YAMAZAKI, Yasuhide YAKUSHI
  • Patent number: 10329687
    Abstract: To reduce ungrown region or abnormal grain growth region in growing a Group III nitride semiconductor through a flux method. A seed substrate has a structure in which a Group III nitride semiconductor layer is formed on a ground substrate as a base, and a mask is formed on the Group III nitride semiconductor layer. The mask has a plurality of dotted windows in an equilateral triangular lattice pattern. A Group III nitride semiconductor is grown through flux method on the seed substrate. Carbon is placed on a lid of a crucible holing the seed substrate and a molten mixture so that carbon is not contact with the molten mixture at the start of crystal growth. Thereby, carbon is gradually added to the molten mixture as time passes. Thus, ungrown region or abnormal grain growth region is reduced in the Group III nitride semiconductor crystal grown on the seed substrate.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: June 25, 2019
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Miki Moriyama, Shiro Yamazaki, Yasuhide Yakushi
  • Publication number: 20180066378
    Abstract: To reduce ungrown region or abnormal grain growth region in growing a Group III nitride semiconductor through a flux method. A seed substrate has a structure in which a Group III nitride semiconductor layer is formed on a ground substrate as a base, and a mask is formed on the Group III nitride semiconductor layer. The mask has a plurality of dotted windows in an equilateral triangular lattice pattern. A Group III nitride semiconductor is grown through flux method on the seed substrate. Carbon is placed on a lid of a crucible holing the seed substrate and a molten mixture so that carbon is not contact with the molten mixture at the start of crystal growth. Thereby, carbon is gradually added to the molten mixture as time passes. Thus, ungrown region or abnormal grain growth region is reduced in the Group III nitride semiconductor crystal grown on the seed substrate.
    Type: Application
    Filed: September 6, 2017
    Publication date: March 8, 2018
    Inventors: Miki MORIYAMA, Shiro YAMAZAKI, Yasuhide YAKUSHI
  • Patent number: 9691610
    Abstract: The present invention provides a method for producing a Group III nitride semiconductor crystal and a GaN substrate, in which the transfer of dislocation density or the occurrence of cracks can be certainly reduced on a growth substrate, and the Group III nitride semiconductor crystal can be easily separated from a seed crystal. A mask layer is formed on a GaN substrate, to thereby form an exposed portion of the GaN substrate, and an unexposed portion of the GaN substrate. Through a flux method, a GaN layer is formed on the exposed portions of the GaN substrate in a molten mixture containing at least Group III metal and Na. At that time, non-crystal portions containing the components of the molten mixture are formed on the mask layer so as to be covered with the GaN layer grown on the GaN substrate and the mask layer.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: June 27, 2017
    Assignee: TOYODA GOSEI CO., LTD
    Inventors: Shohei Kumegawa, Yasuhide Yakushi, Seiji Nagai, Miki Moriyama
  • Patent number: 9263258
    Abstract: Provided is a method for producing a Group III nitride-based compound semiconductor having an M-plane main surface. The method employs a sapphire substrate having a main surface which is inclined by 30° with respect to R-plane about a line of intersection Lsapph-AM formed by R-plane and A-plane perpendicular thereto. R-plane surfaces of the sapphire substrate are exposed, and a silicon dioxide mask is formed on the main surface of the substrate. AlN buffer layers are formed on the exposed R-plane surfaces. A GaN layer is formed on the AlN buffer layers. At an initial stage of GaN growth, the top surface of the sapphire substrate is entirely covered with the GaN layer through lateral growth.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: February 16, 2016
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Seiji Nagai, Shiro Yamazaki, Takayuki Sato, Yasuhide Yakushi, Koji Okuno, Koichi Goshonoo
  • Patent number: 9153439
    Abstract: A mask layer is formed on a Ga polarity surface of the GaN substrate as a growth substrate. Subsequently, a protective film PF is formed on a N polarity surface of the GaN substrate. Then, a plurality of concave portions is formed from the mask layer extending to the GaN substrate, to thereby form a seed crystal. The seed crystal is etched in a Na melt, and a plurality of concave portions having a facet plane exposed. The seed crystal and the raw materials are placed in a crucible, and the pressure and temperature inside the crucible are increased. Thus, a target GaN layer is grown in the upward direction on the surface of the mask layer and the lateral direction over the concave portions.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: October 6, 2015
    Assignee: Toyoda Gosei Co., Ltd
    Inventors: Shohei Kumegawa, Yasuhide Yakushi, Seiji Nagai, Miki Moriyama
  • Publication number: 20140363954
    Abstract: A mask layer is formed on a Ga polarity surface of the GaN substrate as a growth substrate. Subsequently, a protective film PF is formed on a N polarity surface of the GaN substrate. Then, a plurality of concave portions is formed from the mask layer extending to the GaN substrate, to thereby form a seed crystal. The seed crystal is etched in a Na melt, and a plurality of concave portions having a facet plane exposed. The seed crystal and the raw materials are placed in a crucible, and the pressure and temperature inside the crucible are increased. Thus, a target GaN layer is grown in the upward direction on the surface of the mask layer and the lateral direction over the concave portions.
    Type: Application
    Filed: June 10, 2014
    Publication date: December 11, 2014
    Inventors: Shohei Kumegawa, Yasuhide Yakushi, Seiji Nagai, Miki Moriyama
  • Publication number: 20140360426
    Abstract: The present invention provides a method for producing a Group III nitride semiconductor crystal and a GaN substrate, in which the transfer of dislocation density or the occurrence of cracks can be certainly reduced on a growth substrate, and the Group III nitride semiconductor crystal can be easily separated from a seed crystal. A mask layer is formed on a GaN substrate, to thereby form an exposed portion of the GaN substrate, and an unexposed portion of the GaN substrate. Through a flux method, a GaN layer is formed on the exposed portions of the GaN substrate in a molten mixture containing at least Group III metal and Na. At that time, non-crystal portions containing the components of the molten mixture are formed on the mask layer so as to be covered with the GaN layer grown on the GaN substrate and the mask layer.
    Type: Application
    Filed: June 3, 2014
    Publication date: December 11, 2014
    Applicant: TOYODA GOSEI CO., LTD.
    Inventors: Shohei Kumegawa, Yasuhide Yakushi, Seiji Nagai, Miki Moriyama
  • Patent number: 8507364
    Abstract: An object of the present invention is to realize, by the flux process, the production of a high-quality n-type semiconductor crystal having high concentration of electrons. The method of the invention for producing an n-type Group III nitride-based compound semiconductor by the flux process, the method including preparing a melt by melting at least a Group III element by use of a flux; supplying a nitrogen-containing gas to the melt; and growing an n-type Group III nitride-based compound semiconductor crystal on a seed crystal from the melt. In the method, carbon and germanium are dissolved in the melt, and germanium is incorporated as a donor into the semiconductor crystal, to thereby produce an n-type semiconductor crystal. The mole percentage of germanium to gallium in the melt is 0.05 mol % to 0.5 mol %, and the mole percentage of carbon to sodium is 0.1 mol % to 3.0 mol %.
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: August 13, 2013
    Assignees: Toyoda Gosei Co., Ltd., NGK Insulators, Ltd., Osaka University
    Inventors: Seiji Nagai, Shiro Yamazaki, Yasuhide Yakushi, Takayuki Sato, Makoto Iwai, Katsuhiro Imai, Yusuke Mori, Yasuo Kitaoka
  • Publication number: 20090294909
    Abstract: An object of the present invention is to realize, by the flux process, the production of a high-quality n-type semiconductor crystal having high concentration of electrons. The method of the invention for producing an n-type Group III nitride-based compound semiconductor by the flux process, the method including preparing a melt by melting at least a Group III element by use of a flux; supplying a nitrogen-containing gas to the melt; and growing an n-type Group III nitride-based compound semiconductor crystal on a seed crystal from the melt. In the method, carbon and germanium are dissolved in the melt, and germanium is incorporated as a donor into the semiconductor crystal, to thereby produce an n-type semiconductor crystal. The mole percentage of germanium to gallium in the melt is 0.05 mol % to 0.5 mol %, and the mole percentage of carbon to sodium is 0.1 mol % to 3.0 mol %.
    Type: Application
    Filed: May 20, 2009
    Publication date: December 3, 2009
    Applicant: OSAKA UNIVERSITY
    Inventors: Seiji Nagai, Shiro Yamazaki, Yasuhide Yakushi, Takayuki Sato, Makoto Iwai, Katsuhiro Imai, Yusuke Mori, Yasuo Kitaoka
  • Publication number: 20090197118
    Abstract: Provided is a method for producing a Group III nitride-based compound semiconductor having an M-plane main surface. The method employs a sapphire substrate having a main surface which is inclined by 30° with respect to R-plane about a line of intersection Lsapph-AM formed by R-plane and A-plane perpendicular thereto. R-plane surfaces of the sapphire substrate are exposed, and a silicon dioxide mask is formed on the main surface of the substrate. AlN buffer layers are formed on the exposed R-plane surfaces. A GaN layer is formed on the AlN buffer layers. At an initial stage of GaN growth, the top surface of the sapphire substrate is entirely covered with the GaN layer through lateral growth.
    Type: Application
    Filed: January 30, 2009
    Publication date: August 6, 2009
    Applicant: TOYODA GOSEI CO.,LTD.
    Inventors: Seiji NAGAI, Shiro YAMAZAKI, Takayuki SATO, Yasuhide YAKUSHI, Koji OKUNO, Koichi GOSHONOO