Patents by Inventor Yasuhiko Matsunaga

Yasuhiko Matsunaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7969882
    Abstract: In a packet communication network in which the minimum guaranteed rate and maximum limiting rate of packet transfer are contracted for each service, this invention classifies flows corresponding to received packets into group 1 to which a flow whose packet transfer rate is less than the minimum guaranteed rate belongs, group 2 to which a flow whose packet transfer rate is equal to or higher than the minimum guaranteed rate and less than the maximum limiting rate belongs, and group 3 to which a flow whose packet transfer rate exceeds the maximum limiting rate belongs.
    Type: Grant
    Filed: February 6, 2002
    Date of Patent: June 28, 2011
    Assignee: NEC Corporation
    Inventor: Yasuhiko Matsunaga
  • Publication number: 20110018046
    Abstract: A method of manufacturing a semiconductor device including forming two first gate electrodes along a first direction on a first surface of a semiconductor substrate and source/drain areas sandwiching a channel region under each of the first gate electrodes, forming a first interlayer insulating layer to fill a region between the first gate electrodes, lowering a top of the first interlayer insulating layer, depositing a second interlayer insulating layer on the first interlayer insulating layer and the first gate electrodes, planarizing a surface of the second interlayer insulating layer, and forming an interconnect layer in the second interlayer insulating layer and a contact plug in the first interlayer insulating layer and the second interlayer insulating layer so that the contact plug is in contact with the interconnect layer and one of the source/drain areas.
    Type: Application
    Filed: October 7, 2010
    Publication date: January 27, 2011
    Inventors: Hiroyuki KUTSUKAKE, Yasuhiko MATSUNAGA, Shoichi MIYAZAKI
  • Publication number: 20110021238
    Abstract: Terminals and base stations belonging to service areas 100 to 102 of plural radio operators periodically measure a radio-link quality and an availability ratio of a radio link to notify them to a radio-resource management server 40. The server 40 alters a frequency of the base station, and a transmitted-power quantity of the base station and the terminal based on these measured results to improve the radio-link quality, and reduces interference with a neighboring radio system. When a load is concentrated on a network of a specific radio operator, an instruction of handover is given to the terminal from the server 40 to realize a load distribution within the radio operator, and between the radio operators.
    Type: Application
    Filed: September 15, 2010
    Publication date: January 27, 2011
    Applicant: NEC CORPORATION
    Inventor: Yasuhiko Matsunaga
  • Publication number: 20110021156
    Abstract: Provided is a technique of calculating a proper margin according to the area or a radio propagation estimation method in the area design of wireless communication using a radio propagation simulator. From a storage part wherein information relating to positions where deterioration of a communication quality or a radio quality is confirmed and information relating to the radio conditions at the positions are associated with each other, a margin design system extracts positions where the radio conditions are equal, estimates the radio quality at the positions by the radio propagation simulator, and calculates the margin of a radio quality estimated value on the basis of the estimated radio quality.
    Type: Application
    Filed: March 18, 2009
    Publication date: January 27, 2011
    Applicant: NEC CORPORATION
    Inventors: Kosei Kobayashi, Yasuhiko Matsunaga, Yoshinori Watanabe
  • Publication number: 20110014941
    Abstract: Terminals and base stations belonging to service areas 100 to 102 of plural radio operators periodically measure a radio-link quality and an availability ratio of a radio link to notify them to a radio-resource management server 40. The server 40 alters a frequency of the base station, and a transmitted-power quantity of the base station and the terminal based on these measured results to improve the radio-link quality, and reduces interference with a neighboring radio system. When a load is concentrated on a network of a specific radio operator, an instruction of handover is given to the terminal from the server 40 to realize a load distribution within the radio operator, and between the radio operators.
    Type: Application
    Filed: September 15, 2010
    Publication date: January 20, 2011
    Applicant: NEC CORPORATION
    Inventor: Yasuhiko Matsunaga
  • Publication number: 20100314677
    Abstract: A non-volatile semiconductor storage device includes: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate; a first device isolation/insulation film formed in a trench, the trench formed in the semiconductor layer, with a first direction taken as a longitudinal direction; a device formation region formed by separating the semiconductor layer by the first device isolation/insulation film with the first direction taken as a longitudinal direction; and a memory transistor disposed on the device formation region. The first device isolation/insulation film and the device formation region have an impurity of a first conductivity type. An impurity concentration of the impurity of the first conductivity type in the first device isolation/insulation film is higher than that in the device formation region.
    Type: Application
    Filed: March 16, 2010
    Publication date: December 16, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiko KATO, Hiroyuki Kutsukake, Kikuko Sugimae, Yasuhiko Matsunaga
  • Publication number: 20100284293
    Abstract: Provided is a communication network quality analysis technique which can identify a network side communication device, a communication area, or a terminal which causes degradation of quality of the communication network detected by an abnormal communication quality index. The technique analyzes a recording content of a call process performed by the network side communication device and acquires a distribution of quality degradation amounts in respective hierarchies such as a terminal, a network communication device, or a communication area. Thus, the technique estimates a terminal, a network side communication device, or a communication area causing degradation of the communication quality according to a degree of quality degradation degree distribution bias considering the belonging relationship of the terminal, the network side communication device, and the communication area.
    Type: Application
    Filed: December 16, 2008
    Publication date: November 11, 2010
    Applicant: NEC CORPORATION
    Inventors: Yoshinori Watanabe, Yasuhiko Matsunaga, Kosei Kobayashi
  • Patent number: 7825497
    Abstract: A method of manufacturing a semiconductor device including forming two first gate electrodes along a first direction on a first surface of a semiconductor substrate and source/drain areas sandwiching a channel region under each of the first gate electrodes, forming a first interlayer insulating layer to fill a region between the first gate electrodes, lowering a top of the first interlayer insulating layer, depositing a second interlayer insulating layer on the first interlayer insulating layer and the first gate electrodes, planarizing a surface of the second interlayer insulating layer, and forming an interconnect layer in the second interlayer insulating layer and a contact plug in the first interlayer insulating layer and the second interlayer insulating layer so that the contact plug is in contact with the interconnect layer and one of the source/drain areas.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: November 2, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Kutsukake, Yasuhiko Matsunaga, Shoichi Miyazaki
  • Patent number: 7826796
    Abstract: Terminals and base stations belonging to service areas 100 to 102 of plural radio operators periodically measure a radio-link quality and an availability ratio of a radio link to notify them to a radio-resource management server 40. The server 40 alters a frequency of the base station, and a transmitted-power quantity of the base station and the terminal based on these measured results to improve the radio-link quality, and reduces interference with a neighboring radio system. When a load is concentrated on a network of a specific radio operator, an instruction of handover is given to the terminal from the server 40 to realize a load distribution within the radio operator, and between the radio operators.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: November 2, 2010
    Assignee: NEC Corporation
    Inventor: Yasuhiko Matsunaga
  • Publication number: 20100273493
    Abstract: A radio access network management device capable of estimating the resource utilization ratio of an additionally installed radio base station to predict the date on which the next additional installation is required. The radio access network management device comprises a means for obtaining traffic demand per unit area for existing radio cells around the position at which a radio base station is additionally installed from the coverage of the existing radio cells and the time series of the past communication traffic statistics, a means for estimating the coverage of the radio cells after the additional installation of the radio base station, a means for predicting the traffic demand of the radio cells after the additional installation thereof from the coverage and traffic demand per unit area, and a means for predicting future communication quality from the predicted traffic demand.
    Type: Application
    Filed: December 8, 2008
    Publication date: October 28, 2010
    Inventors: Yasuhiko Matsunaga, Yoshinori Watanabe, Kosei Kobayashi
  • Publication number: 20100238733
    Abstract: A NAND flash memory includes a NAND string and a control circuit, wherein in a write operation, the control circuit applies a writing voltage between a control gate of a selected memory cell to be written and a semiconductor well, and after the write operation and before performing a verification read operation of verifying whether data has been written into the selected memory cell, the control circuit performs a de-trapping operation, in which a first voltage of a same potential as that of the semiconductor well or a same polarity as that of the writing voltage is applied to the control gate of the selected memory cell and in which a second voltage of a same polarity as that of the writing voltage and larger than the first voltage as an absolute value is applied to a control gate of unselected memory cells not to be written.
    Type: Application
    Filed: March 19, 2010
    Publication date: September 23, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koichi FUKUDA, Yasuhiko Matsunaga
  • Patent number: 7782675
    Abstract: A semiconductor memory device includes a memory cell array which includes a plurality of memory cell strings each including a plurality of memory cells and a first dummy cell, which have current paths connected in series at one end and the other end thereof, a plurality of first and second select transistors, a source line, and a bit line, wherein the first dummy cell is disposed on the source line side such that one end and the other end of the current path thereof are connected between the first select transistor and the memory cell, and a threshold voltage of the first dummy cell is higher than a neutral threshold voltage.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: August 24, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiko Matsunaga, Fumitaka Arai
  • Patent number: 7772102
    Abstract: A nonvolatile semiconductor memory that allows simultaneous implementation of high performance transistors in a low-voltage circuit region and transistors with high withstand voltages in a high-voltage circuit region.
    Type: Grant
    Filed: June 8, 2009
    Date of Patent: August 10, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yasuhiko Matsunaga
  • Publication number: 20100176422
    Abstract: A semiconductor memory device includes a semiconductor substrate; a memory cell array on the semiconductor substrate, the memory cell array comprising a plurality of memory cells capable of electrically storing data; a sense amplifier configured to detect the data stored in at least one of the memory cells; a cell source driver electrically connected to source side terminals of the memory cells and configured to supply a source potential to at least one of the source side terminals of the memory cells; a first wiring configured to electrically connect between at least one of the source side terminals of the memory cells and the cell source driver; and a second wiring formed in a same wiring layer as the first wiring, the second wiring being insulated from the first wiring and being electrically connected to the sense amplifier, wherein the first wiring and the second wiring have a plurality of through holes provided at a predetermined interval.
    Type: Application
    Filed: December 30, 2009
    Publication date: July 15, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Koichi FUKUDA, Dai NAKAMURA, Yasuhiko MATSUNAGA
  • Publication number: 20100174945
    Abstract: A failure cause analysis system for estimating a cause of a failure in a communication network from recorded contents of internal processing of a communication apparatus includes: feature extraction means for extracting a statistical feature of the recorded contents at a time of occurrence of a failure; and failure cause estimation means for estimating a failure cause based on similarity between a statistical feature of the recorded contents that is acquired at a time of occurrence of a past failure with a known failure cause and the statistical feature of the recorded contents that is acquired at the time of occurrence of the failure.
    Type: Application
    Filed: June 6, 2008
    Publication date: July 8, 2010
    Applicant: NEC CORPORATION
    Inventors: Yoshinori Watanabe, Yasuhiko Matsunaga
  • Publication number: 20100173471
    Abstract: A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, a first and a second control gate electrode layer, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on the high voltage gate insulating film, a second inter-gate insulating film having an aperture, a third and a fourth control gate electrode layer, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on the second tunneling insulating film, a third inter-gate insulating film having an aperture, a fifth and a sixth control gate electrode layer, and a third metallic silicide film; and a liner insulating film directly disposed on a first source and drain region of the memory cell transistor, a second source and drain region of the low voltage transistor, and a third source and drain region
    Type: Application
    Filed: March 9, 2010
    Publication date: July 8, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kikuko Sugimae, Masayuki Ichige, Fumitaka Arai, Yasuhiko Matsunaga, Atsuhiro Sato
  • Patent number: 7750417
    Abstract: A non-volatile semiconductor memory includes memory cell transistors arranged in a matrix, wherein each of the memory cell transistors is a depletion mode MIS transistor.
    Type: Grant
    Filed: August 1, 2007
    Date of Patent: July 6, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naohisa Iino, Yasuhiko Matsunaga, Fumitaka Arai
  • Patent number: 7745884
    Abstract: A nonvolatile semiconductor memory of an aspect of the present invention comprises a plurality of memory cell transistors which are connected in series to one another with a first gate spacing, every two adjacent transistors of the memory cell transistors sharing a source/drain diffusion layer, and a first select gate transistor which shares a source/drain diffusion layer with an endmost memory cell transistor that is located at one end of the series connection of the memory cell transistors and is adjacent to that memory cell transistor with a second gate spacing. The second gate spacing is set larger than the first gate spacing and the source/drain diffusion layer shared by the endmost memory cell transistor and the first select gate transistor contains a region which is higher in impurity concentration than the source/drain diffusion layer shared by two adjacent memory cell transistors.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: June 29, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuhiro Sato, Fumitaka Arai, Yasuhiko Matsunaga
  • Patent number: 7734255
    Abstract: The radio resource management server 1 receives radio link quality information measured by the radio base station 2 and radio link quality information measured by the radio base station 3 and thus detects the occurrence of interference. Upon the occurrence of the interference, the transmission power of the radio base station causing the occurrence of interference is controllably reduced to suppress the interference. In the method of controllably varying the transmission power of a radio base station, depending on the number of radio terminals or traffic volume, oscillation of a service area occurs. However, according to the present invention, the transmission power is changed on the occurrence of interference, without depending on the number of radio terminals or traffic volume, so that the area oscillation does not occur after the transmission power has been once stabilized.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: June 8, 2010
    Assignee: NEC Corporation
    Inventor: Yasuhiko Matsunaga
  • Patent number: 7728435
    Abstract: A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has a bottom in the second barrier film. The bottom has a width greater than a trench made in the first insulation layer, as measured in a direction crossing the widthwise direction of the trench. The lower contact hole penetrates the first insulation layer and first barrier film, communicates with the first contact hole via the trench and is provided on the diffusion layer. The upper portion of the lower contact hole has the same width as the trench. The contact plug is provided in the upper contact hole and lower contact hole.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: June 1, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Sakuma, Yasuhiko Matsunaga, Fumitaka Arai, Kikuko Sugimae