Patents by Inventor Yasuhiko Taniguchi

Yasuhiko Taniguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150040355
    Abstract: A cleaner for a fiber bundle feeder, which nips and discharges a strip of fiber bundle with a top roller and a bottom roller, in a fore-spinning frame includes a support member located above the top roller and a tubular clearer having an inner diameter that is greater than an outer diameter of the support member. The tubular clearer is rotatable around the support member by the top roller such that the tubular clearer is located at a position where the tubular clearer is in contact with the top roller and a position where the tubular clearer is separated from the top roller. The tubular clearer is configured to block a fiber. A suction unit is configured to draw in the fiber that has been blocked by the tubular clearer.
    Type: Application
    Filed: August 8, 2014
    Publication date: February 12, 2015
    Applicant: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
    Inventors: Makoto YAKUSHI, Yasuhiko TANIGUCHI
  • Patent number: 7263766
    Abstract: An insulating substrate (1) has insulative ceramic layers (2, 3) laid one upon another, an intermediate layer (4) made of a material that is different from a material of the ceramic layers and arranged between adjacent ones of the ceramic layers to join the adjacent ceramic layers to each other, a first conductive layer (5) joined to the top surface of a top one of the ceramic layers, and a second conductive layer (6) joined to the bottom surface of a bottom one of the ceramic layers. Even if any one of the ceramic layers has strength lower than design strength and causes a breakage due to, for example, thermal stress, the remaining ceramic layers are sound to secure a specified breakdown voltage for the insulating substrate.
    Type: Grant
    Filed: January 27, 2003
    Date of Patent: September 4, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yutaka Ishiwata, Kosoku Nagata, Toshio Shimizu, Hiroyuki Hiramoto, Yasuhiko Taniguchi, Kouji Araki, Hiroshi Fukuyoshi, Hiroshi Komorita
  • Publication number: 20030168729
    Abstract: An insulating substrate (1) has insulative ceramic layers (2, 3) laid one upon another, an intermediate layer (4) made of a material that is different from a material of the ceramic layers and arranged between adjacent ones of the ceramic layers to join the adjacent ceramic layers to each other, a first conductive layer (5) joined to the top surface of a top one of the ceramic layers, and a second conductive layer (6) joined to the bottom surface of a bottom one of the ceramic layers. Even if any one of the ceramic layers has strength lower than design strength and causes a breakage due to, for example, thermal stress, the remaining ceramic layers are sound to secure a specified breakdown voltage for the insulating substrate.
    Type: Application
    Filed: January 27, 2003
    Publication date: September 11, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yutaka Ishiwata, Kosoku Nagata, Toshio Shimizu, Hiroyuki Hiramoto, Yasuhiko Taniguchi, Kouji Araki, Hiroshi Fukuyoshi, Hiroshi Komorita
  • Patent number: 6605868
    Abstract: An insulating substrate (1) has insulative ceramic layers (2, 3) laid one upon another, an intermediate layer (4) made of a material that is different from a material of the ceramic layers and arranged between adjacent ones of the ceramic layers to join the adjacent ceramic layers to each other, a first conductive layer (5) joined to the top surface of a top one of the ceramic layers, and a second conductive layer (6) joined to the bottom surface of a bottom one of the ceramic layers. Even if any one of the ceramic layers has strength lower than design strength and causes a breakage due to, for example, thermal stress, the remaining ceramic layers are sound to secure a specified breakdown voltage for the insulating substrate.
    Type: Grant
    Filed: December 9, 1999
    Date of Patent: August 12, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yutaka Ishiwata, Kosoku Nagata, Toshio Shimizu, Hiroyuki Hiramoto, Yasuhiko Taniguchi, Kouji Araki, Hiroshi Fukuyoshi, Hiroshi Komorita
  • Publication number: 20020066953
    Abstract: An insulating substrate (1) has insulative ceramic layers (2, 3) laid one upon another, an intermediate layer (4) made of a material that is different from a material of the ceramic layers and arranged between adjacent ones of the ceramic layers to join the adjacent ceramic layers to each other, a first conductive layer (5) joined to the top surface of a top one of the ceramic layers, and a second conductive layer (6) joined to the bottom surface of a bottom one of the ceramic layers. Even if any one of the ceramic layers has strength lower than design strength and causes a breakage due to, for example, thermal stress, the remaining ceramic layers are sound to secure a specified breakdown voltage for the insulating substrate.
    Type: Application
    Filed: December 9, 1999
    Publication date: June 6, 2002
    Inventors: YUTAKA ISHIWATA, KOSOKU NAGATA, TOSHIO SHIMIZU, HIROYUKI HIRAMOTO, YASUHIKO TANIGUCHI, KOUJI ARAKI, HIROSHI FUKUYOSHI, HIROSHI KOMORITA
  • Patent number: 6344789
    Abstract: A voltage non-linear resistor unit is composed of at least one of voltage non-linear resistors which is composed of a columnar sintered body formed by molding and sintering a raw material, the sintered body having both end surfaces having a surface roughness in term of arithmetic average surface roughness Ra of 1 to 2 &mgr;m and being formed with an electrode film layer, a terminal metal fitting formed in a predetermined shape and attached to the voltage non-linear resistor, and a soldering material arranged between the voltage non-linear resistors and between joint surfaces of the voltage non-linear resistor and the terminal metal fitting, the joint surfaces being joined by heating the soldering material and applying a load vertically to the joint surfaces while giving a rotation motion thereto. Such voltage non-linear resistor is effectively assembled into an arrester.
    Type: Grant
    Filed: July 14, 2000
    Date of Patent: February 5, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Udagawa, Masahiro Kan, Yoshihiro Ishizaki, Nobuyuki Shimizu, Hironori Suzuki, Hiroyoshi Narita, Yoshihiko Hirano, Hideyasu Andoh, Yasuhiko Taniguchi, Masahiro Hanai, Masahiko Ebina, Keisuke Shimagami, Yoshiyasu Itoh, Takahiko Shindo