Abstract: A semiconductor device includes an effective pattern region and at least one measurement mark region. The measurement mark region includes a measuring objective portion. The measuring objective portion has the same shape as a portion forming part of the effective pattern region.

Abstract: A semiconductor memory device has a plurality of memory block areas, a first power source line and a second power source line for supplying the same potential as the first power source line. At least one of the memory block areas is connected to the first power source line, and at least one of the other memory block areas is connected to the second power source line. For example, when the semiconductor memory device includes four memory block areas, one of two memory block areas simultaneously selected is connected to the first power source line, and the other is connected to the second power source line. Further, one of the other two memory block areas simultaneously selected is connected to the first power source line and the other is connected to the second power source line.

Abstract: The positions of first terminals of a first semiconductor chip have a plane symmetrical relationship with the positions of second terminals of a second semiconductor chip. First buffer circuits of the first semiconductor chip are identical with second buffer circuits of the second semiconductor chip at least in design. First and second internal circuits are identical with each other at least in design. The first and second semiconductor chips have different interconnecting lines.

Abstract: A semiconductor memory device has a plurality of memory block areas, a first power source line and a second power source line for supplying the same potential as the first power source line. At least one of the memory block areas is connected to the first power source line, and at least one of the other memory block areas is connected to the second power source line. For example, when the semiconductor memory device includes four memory block areas, one of two memory block areas simultaneously selected is connected to the first power source line, and the other is connected to the second power source line. Further, one of the other two memory block areas simultaneously selected is connected to the first power source line and the other is connected to the second power source line.

Abstract: A semiconductor device includes an effective pattern region and at least one measurement mark region. The measurement mark region includes a measuring objective portion. The measuring objective portion has the same shape as a portion forming part of the effective pattern region.

Abstract: The positions of first terminals of a first semiconductor chip have a plane symmetrical relationship with the positions of second terminals of a second semiconductor chip. First buffer circuits of the first semiconductor chip are identical with second buffer circuits of the second semiconductor chip at least in design. First and second internal circuits are identical with each other at least in design. The first and second semiconductor chips have different interconnecting lines.

Abstract: A semiconductor storage device which can prevent a short-circuit current from flowing therethrough even if a short circuit occurs between main word lines and bit lines. The semiconductor storage device has a plurality of normal memory cell array blocks, each including multiple columns of bit line pairs, sub word lines and normal memory cells. The semiconductor storage device also includes main word lines extending through the plurality of normal memory cell array blocks, a main row selecting decoder for selecting one of the main word lines on the basis of a main row address signal, a sub row selecting decoder for selecting one of the sub word lines depending on one of the main word lines on the basis of a sub row address signal, and a pre-charge circuit for pre-charging a pair of bit lines.