Patents by Inventor Yasuhiko Tsukikawa
Yasuhiko Tsukikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11200945Abstract: A plurality of memory cells are arranged along a plurality of bit lines and a plurality of word lines. A sense amplifier is connected to each of the bit lines. Arranged along each bit line are at least four memory cells including first to fourth memory cells that are either connected to or disconnected from one of the bit lines by means of first to fourth switching elements according to an active or inactive state of first to fourth word lines. The first memory cell stores a first bit value, the second memory cell stores a second bit value, and the third and fourth memory cells each store a third bit value. A memory cell array control circuit activates and then deactivates the third and fourth word lines, subsequently activates the first and second word lines, and then activates the sense amplifier.Type: GrantFiled: January 31, 2017Date of Patent: December 14, 2021Assignee: ZENTEL JAPAN CORPORATIONInventors: Takashi Kubo, Masaru Haraguchi, Takeshi Hamamoto, Kenichi Yasuda, Yasuhiko Tsukikawa, Hironori Iga
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Patent number: 10991418Abstract: A control device of the invention for a semiconductor memory device comprising an interface conforming to JEDEC standard of DDRx-SDRAM or LPDDRx-SDRAM, comprises banks, a read/write control circuit, and a transfer control circuit. Each bank comprises subarrays. Each subarray comprises memory cells arranged along bit lines and word lines. The read/write control circuit controls reading of data from and writing of data to the semiconductor memory device. The transfer control circuit controls data transfer inside the semiconductor memory device and sets to enable an additional transfer command not specified in the JEDEC standard and a transfer command for writing data, read from a transfer source memory cell, to a transfer destination memory cell without passing outside the semiconductor memory device by transmitting a first signal value not used in the JEDEC standard to the semiconductor memory device via at least one signal line of the interface.Type: GrantFiled: March 6, 2017Date of Patent: April 27, 2021Assignee: ZENTEL JAPAN CORPORATIONInventors: Masaru Haraguchi, Takashi Kubo, Yasuhiko Tsukikawa, Hironori Iga, Kenichi Yasuda, Takeshi Hamamoto
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Publication number: 20200135261Abstract: According to a control device of a first aspect of the invention, for a semiconductor memory device comprising an interface conforming to JEDEC (Joint Electron Device Engineering Council) standard of DDRx-SDRAM or LPDDRx-SDRAM, the control device comprises a plurality of banks, a read/write control circuit, and a transfer control circuit. The banks are connected to one another by an internal data bus, and each bank, separated from one another by at least one sense amplifier row comprising a plurality of sense amplifiers, comprises a plurality of subarrays. Each subarray comprises a plurality of memory cells arranged along a plurality of bit lines and a plurality of word lines orthogonal to the bit lines. The read/write control circuit controls reading of data from the semiconductor memory device and writing of data to the semiconductor memory device.Type: ApplicationFiled: March 6, 2017Publication date: April 30, 2020Inventors: Masaru Haraguchi, Takashi Kubo, Yasuhiko Tsukikawa, Hironori Iga, Kenichi Yasuda, Takeshi Hamamoto
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Publication number: 20190378561Abstract: A plurality of memory cells are arranged along a plurality of bit lines and a plurality of word lines. A sense amplifier is connected to each of the bit lines. Arranged along each bit line are at least four memory cells including first to fourth memory cells that are either connected to or disconnected from one of the bit lines by means of first to fourth switching elements according to an active or inactive state of first to fourth word lines. The first memory cell stores a first bit value, the second memory cell stores a second bit value, and the third and fourth memory cells each store a third bit value. A memory cell array control circuit activates and then deactivates the third and fourth word lines, subsequently activates the first and second word lines, and then activates the sense amplifier.Type: ApplicationFiled: January 31, 2017Publication date: December 12, 2019Inventors: TAKASHI KUBO, MASARU HARAGUCHI, TAKESHI HAMAMOTO, KENICHI YASUDA, YASUHIKO TSUKIKAWA, HIRONORI IGA
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Patent number: 7288965Abstract: A level conversion circuit that converts a signal outputted from a second internal circuit receiving a first power supply voltage to a signal of a level of a second power supply voltage having a voltage level different than the first power supply voltage to apply its output signal to a first internal circuit, is provided with a mechanism for cutting off a path passing a through current in the level conversion circuit when the first power supply voltage is cut off.Type: GrantFiled: December 21, 2006Date of Patent: October 30, 2007Assignee: Renesas Technology Corp.Inventors: Kyoji Yamasaki, Yasuhiko Tsukikawa
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Publication number: 20070103197Abstract: A level conversion circuit that converts a signal outputted from a second internal circuit receiving a first power supply voltage to a signal of a level of a second power supply voltage having a voltage level different than the first power supply voltage to apply its output signal to a first internal circuit, is provided with a mechanism for cutting off a path passing a through current in the level conversion circuit when the first power supply voltage is cut off.Type: ApplicationFiled: December 21, 2006Publication date: May 10, 2007Applicant: Renesas Technology Corp.Inventors: Kyoji Yamasaki, Yasuhiko Tsukikawa
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Patent number: 7161387Abstract: A level conversion circuit that converts a signal outputted from a second internal circuit receiving a first power supply voltage to a signal of a level of a second power supply voltage having a voltage level different than the first power supply voltage to apply its output signal to a first internal circuit, is provided with a mechanism for cutting off a path passing a through current in the level conversion circuit when the first power supply voltage is cut off.Type: GrantFiled: September 23, 2004Date of Patent: January 9, 2007Assignee: Renesas Technology Corp.Inventors: Kyoji Yamasaki, Yasuhiko Tsukikawa
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Patent number: 7102935Abstract: Independent power supply systems are provided for a peripheral circuit other than a column decoder, an array-relevant circuit, and a column decoder respectively, so that a peripheral power supply voltage, an array power supply voltage, and a column decoder power supply voltage generated independently of each other are supplied to the peripheral circuit, the array-relevant circuit, and the column decoder as an operating power supply voltage, respectively. Preferably, the column decoder power supply voltage during normal operation is set as an intermediate voltage between the peripheral power supply voltage and the array power supply voltage. Thus, an array configuration suitable for driving a transistor with a low voltage in order to achieve lower power consumption can be obtained.Type: GrantFiled: October 26, 2004Date of Patent: September 5, 2006Assignee: Renesas Technology Corp.Inventors: Takeo Miki, Yasuhiko Tsukikawa, Shinji Tanaka
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Patent number: 7072204Abstract: Each cell unit has a cell plate electrically isolated from the cell plates in the other cell units.Type: GrantFiled: May 18, 2005Date of Patent: July 4, 2006Assignee: Renesas Technology Corp.Inventors: Yasuhiko Tsukikawa, Takashi Ito
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Publication number: 20050219893Abstract: Each cell unit has a cell plate electrically isolated from the cell plates in the other cell units.Type: ApplicationFiled: May 18, 2005Publication date: October 6, 2005Applicant: RENESAS TECHNOLOGY CORP.Inventors: Yasuhiko Tsukikawa, Takashi Ito
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Patent number: 6934204Abstract: A P-channel MOS transistor is provided between a terminal and an SVIH detection circuit for performing test mode detection. The P-channel MOS transistor is rendered non-conductive when a potential supplied to the terminal that is used commonly for signal input during the test setting and the normal operation is a power-supply potential EXTVDD or below. The SVIH detection circuit detects that a test mode is to be set when the potential at the terminal becomes higher than a prescribed potential. During the normal operation, the terminal is disconnected from the SVIH detection circuit so that the input capacitance of the terminal can be made to be about the same as that of another input terminal, and a high speed operation becomes possible. Moreover, there is no need to take into account the parasitic capacitance of an interconnection line leading to the SVIH detection circuit.Type: GrantFiled: May 8, 2002Date of Patent: August 23, 2005Assignee: Renesas Technology Corp.Inventors: Takashi Itou, Yasuhiko Tsukikawa
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Patent number: 6903961Abstract: Each of twin-cell units each formed of two DRAM cells has a cell plate electrically isolated from the cell plates in the other twin-cell units. Thereby, voltages on two storage nodes storing mutually complementary data in the same twin-cell unit change similarly to each other owing to capacitive coupling.Type: GrantFiled: June 26, 2003Date of Patent: June 7, 2005Assignee: Renesas Technology Corp.Inventors: Yasuhiko Tsukikawa, Takashi Ito
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Publication number: 20050088881Abstract: Independent power supply systems are provided for a peripheral circuit other than a column decoder, an array-relevant circuit, and a column decoder respectively, so that a peripheral power supply voltage, an array power supply voltage, and a column decoder power supply voltage generated independently of each other are supplied to the peripheral circuit, the array-relevant circuit, and the column decoder as an operating power supply voltage, respectively. Preferably, the column decoder power supply voltage during normal operation is set as an intermediate voltage between the peripheral power supply voltage and the array power supply voltage. Thus, an array configuration suitable for driving a transistor with a low voltage in order to achieve lower power consumption can be obtained.Type: ApplicationFiled: October 26, 2004Publication date: April 28, 2005Inventors: Takeo Miki, Yasuhiko Tsukikawa, Shinji Tanaka
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Publication number: 20050068062Abstract: A level conversion circuit that converts a signal outputted from a second internal circuit receiving a first power supply voltage to a signal of a level of a second power supply voltage having a voltage level different than the first power supply voltage to apply its output signal to a first internal circuit, is provided with a mechanism for cutting off a path passing a through current in the level conversion circuit when the first power supply voltage is cut off.Type: ApplicationFiled: September 23, 2004Publication date: March 31, 2005Inventors: Kyoji Yamasaki, Yasuhiko Tsukikawa
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Patent number: 6867994Abstract: A field region forming a transistor is provided in a direction crossing a word line and a bit line. A bit line contact is provided corresponding to each bit line in a row direction. Storage node contacts are provided in alignment corresponding to respective columns in the row direction. The size of a basic cell region for forming a single memory cell can be set to 2·F·3·F. Here, F represents a minimum design size. Accordingly, memory cells in a twin cell mode DRAM storing one bit of data with two memory cells can be reduced in size.Type: GrantFiled: June 19, 2003Date of Patent: March 15, 2005Assignee: Renesas Technology Corp.Inventor: Yasuhiko Tsukikawa
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Patent number: 6787859Abstract: There is provided a semiconductor memory device including eight memory blocks 20a to 20h, first data bus 22a, and second data bus 22b. The eight memory blocks are arranged at respective eight of the total nine areas 11 to 19 defined in a three rows by three columns matrix except for a center area 19. A first data bus 22a linearly extends between memory blocks in the first and second row of the matrix. A second data bus 22b linearly extends between memory blocks in the second and third row of the matrix. The eight memory blocks includes a first group of the four memory blocks arranged adjacent the first data bus and connected to the first data bus and a second group of the four memory blocks arranged adjacent the second data bus and connected to the second data bus.Type: GrantFiled: August 20, 2002Date of Patent: September 7, 2004Assignee: Renesas Technology Corp.Inventors: Takashi Itou, Masaki Shimoda, Yasuhiko Tsukikawa
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Publication number: 20040156255Abstract: A field region forming a transistor is provided in a direction crossing a word line and a bit line. A bit line contact is provided corresponding to each bit line in a row direction. Storage node contacts are provided in alignment corresponding to respective columns in the row direction. The size of a basic cell region for forming a single memory cell can be set to 2·F·3·F. Here, F represents a minimum design size. Accordingly, memory cells in a twin cell mode DRAM storing one bit of data with two memory cells can be reduced in size.Type: ApplicationFiled: June 19, 2003Publication date: August 12, 2004Applicant: RENESAS TECHNOLOGY CORP.Inventor: Yasuhiko Tsukikawa
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Publication number: 20040141361Abstract: Each of twin-cell units each formed of two DRAM cells has a cell plate electrically isolated from the cell plates in the other twin-cell units. Thereby, voltages on two storage nodes storing mutually complementary data in the same twin-cell unit change similarly to each other owing to capacitive coupling.Type: ApplicationFiled: June 26, 2003Publication date: July 22, 2004Applicant: RENESAS TECHNOLOGY CORP.Inventors: Yasuhiko Tsukikawa, Takashi Ito
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Patent number: 6735133Abstract: In a semiconductor memory circuit including a memory cell array and first and second sense amplifier circuits provided at opposite sides of the memory cell array, respectively and having a plurality of first sense amplifiers and a plurality of second sense amplifiers, respectively, a first bit line and sense amplifier interconnecting circuit, a first bit line equalizing circuit and a first short-circuiting transistor circuit are provided between the memory cell array and the first sense amplifier circuit, while a second bit line and sense amplifier interconnecting circuit, a second bit line equalizing circuit and a second short-circuiting transistor circuit are provided between the memory cell array and the second sense amplifier circuit.Type: GrantFiled: June 12, 2003Date of Patent: May 11, 2004Assignee: Renesas Technology Corp.Inventor: Yasuhiko Tsukikawa
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Patent number: 6727738Abstract: A delay locked loop (DLL) employs a gray code (an alternate code) counter as a delay register. Preventing a carry from arising at more than one bit can minimize skipping of delay time (discontinuous skipping thereof) if a metastable state should occur.Type: GrantFiled: June 11, 2001Date of Patent: April 27, 2004Assignee: Renesas Technology Corp.Inventor: Yasuhiko Tsukikawa