Patents by Inventor Yasuhiro HIRASHIMA
Yasuhiro HIRASHIMA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230352093Abstract: According to one embodiment, a semiconductor memory device includes a first circuit configured to receive first bit data of an input signal, store, in a first latch circuit, first data based on the first bit data and a reference voltage, and output a first signal based on the first data, and a second circuit configured to receive second bit data of the input signal, store, in a second latch circuit, second data based on the second bit data and the reference voltage, and output a second signal based on the second data. The first circuit is configured to set the first latch circuit in a reset state based on the second signal. The second circuit is configured compare the second bit data and the reference voltage based on the first data and set the second latch circuit in a reset state based on the first signal.Type: ApplicationFiled: March 3, 2023Publication date: November 2, 2023Applicant: Kioxia CorporationInventors: Junya MATSUNO, Yasuhiro HIRASHIMA, Toshiyuki KOUCHI
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Publication number: 20230317179Abstract: A semiconductor memory device includes a first pad, a clock generation circuit configured to generate a first clock, an output circuit configured to output the first clock through the first pad, a designation circuit configured to designate one of a plurality of contiguous times slots, each of which is set with respect to clock cycles of the first clock, and a peak control circuit configured to execute an operation that generates a current peak, at a timing corresponding to the designated time slot.Type: ApplicationFiled: August 30, 2022Publication date: October 5, 2023Inventors: Mitsuhiro ABE, Yasuhiro HIRASHIMA, Mitsuaki HONMA
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Patent number: 11769535Abstract: A semiconductor memory device includes a memory cell array, first and second pads, an interface circuit connected to the first pad and configured to transmit data input through the first pad to the memory cell array and output data received from the memory cell array through the first pad, a ZQ calibration circuit that is connected to the second pad and executes a ZQ calibration to generate a ZQ calibration value, and a sequencer configured to control the ZQ calibration circuit to apply the ZQ calibration value to the interface circuit. A command set is input through the first pad after reading data from the memory cell array to cause the interface circuit to output the data read from the memory cell array, and the ZQ calibration circuit executes the ZQ calibration after the command set is input and before the data is output through the first pad.Type: GrantFiled: February 25, 2022Date of Patent: September 26, 2023Assignee: Kioxia CorporationInventor: Yasuhiro Hirashima
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Publication number: 20230297239Abstract: A memory system includes a memory chip and a memory controller. The memory chip includes a storage region that stores setup data used for setup of the memory chip during power on thereof. The memory controller is configured to determine whether or not the memory controller has the setup data, when determining that the memory controller does not have the setup data, instruct the memory chip to read the setup data from the storage region and perform a first setup operation based on the read setup data, and when determining that the memory controller has the setup data, transmit the setup data to the memory chip and instruct the memory chip to perform a second setup operation based on the setup data received from the memory controller.Type: ApplicationFiled: August 29, 2022Publication date: September 21, 2023Inventors: Kenta SHIBASAKI, Yoshihiko SHINDO, Yasuhiro HIRASHIMA, Akio SUGAHARA, Shigeki NAGASAKA, Dai NAKAMURA, Yousuke HAGIWARA
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Publication number: 20230213993Abstract: According to an embodiment, a semiconductor memory device includes a first pin, a first receiving circuit, and a first terminating circuit. The first pin receives a first signal and a second signal having a smaller amplitude than the first signal. The first receiving circuit is connected to the first pin and outputs, based on a comparison between the first signal and a first voltage, a third signal. The first receiving circuit also outputs, based on a comparison between the second signal and a second voltage, a fourth signal having a smaller amplitude than the third signal. The first terminating circuit is connected to the first pin. The first terminating circuit is disabled if the first pin receives the first signal, and enabled if the first pin receives the second signal.Type: ApplicationFiled: March 9, 2023Publication date: July 6, 2023Applicant: Kioxia CorporationInventors: Akio SUGAHARA, Yasuhiro HIRASHIMA, Naoya TOKIWA
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Publication number: 20230188137Abstract: A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.Type: ApplicationFiled: February 6, 2023Publication date: June 15, 2023Inventors: Yasuhiro HIRASHIMA, Masaru KOYANAGI, Yutaka TAKAYAMA
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Patent number: 11621712Abstract: A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.Type: GrantFiled: September 13, 2021Date of Patent: April 4, 2023Assignee: Kioxia CorporationInventors: Yasuhiro Hirashima, Masaru Koyanagi, Yutaka Takayama
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Publication number: 20230078945Abstract: A semiconductor memory device includes a memory cell array, first and second pads, an interface circuit connected to the first pad and configured to transmit data input through the first pad to the memory cell array and output data received from the memory cell array through the first pad, a ZQ calibration circuit that is connected to the second pad and executes a ZQ calibration to generate a ZQ calibration value, and a sequencer configured to control the ZQ calibration circuit to apply the ZQ calibration value to the interface circuit. A command set is input through the first pad after reading data from the memory cell array to cause the interface circuit to output the data read from the memory cell array, and the ZQ calibration circuit executes the ZQ calibration after the command set is input and before the data is output through the first pad.Type: ApplicationFiled: February 25, 2022Publication date: March 16, 2023Inventor: Yasuhiro HIRASHIMA
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Patent number: 11450390Abstract: In a semiconductor integrated circuit, an input circuit includes an input and an output stage electrically connected to the input stage via a first node and a second node. The input stage includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first time constant adjusting circuit, and a second time constant adjusting circuit. The first transistor includes a gate that receives an input signal. The second transistor includes a gate that receives a reference signal. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The first time constant adjusting circuit is electrically connected between a gate of the third transistor and the first node. The second time constant adjusting circuit is electrically connected between a gate of the fourth transistor and the second node.Type: GrantFiled: December 11, 2020Date of Patent: September 20, 2022Assignee: Kioxia CorporationInventors: Fumiya Watanabe, Masaru Koyanagi, Yutaka Shimizu, Yasuhiro Hirashima, Kei Shiraishi, Mikihiko Ito
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Publication number: 20220230665Abstract: According to one embodiment, a semiconductor memory device includes: a first delay circuit configured to delay a first signal and provide a variable delay time; a first select circuit configured to select a second signal or a third signal based on the first signal delayed by the first delay circuit; a first output buffer configured to output a fourth signal based on a signal selected by the first select circuit; a first output pad configured to externally output the fourth signal; and a counter configured to count a number of times the fourth signal is output.Type: ApplicationFiled: April 8, 2022Publication date: July 21, 2022Applicant: Kioxia CorporationInventors: Yasuhiro HIRASHIMA, Mitsuhiro ABE, Norichika ASAOKA
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Patent number: 11218141Abstract: A correction circuit includes a first detection unit, a second detection unit, a delay unit, and a waveform shaping unit. The first detection unit is configured to measure a first period of a high level of a first clock. The second detection unit is configured to measure a second period of a high level of a second clock that is complementary to the first clock. The delay unit is configured to generate a first delay clock and a second delay clock according to a difference between the first period and the second period. The waveform shaping unit is configured to generate a third clock having a logic level which is switched based on an edge of the first delay clock and an edge of the second delay clock.Type: GrantFiled: December 20, 2019Date of Patent: January 4, 2022Assignee: KIOXIA CORPORATIONInventors: Yasuhiro Hirashima, Masaru Koyanagi
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Publication number: 20210409023Abstract: A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.Type: ApplicationFiled: September 13, 2021Publication date: December 30, 2021Inventors: Yasuhiro HIRASHIMA, Masaru KOYANAGI, Yutaka TAKAYAMA
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Patent number: 11211130Abstract: A semiconductor device comprises an input circuit that includes a first comparator configured to output a first output signal and a second output signal having a phase opposite to that of the first output signal, based on a comparison result of a first input signal and a second input signal which is a complementary signal of the first input signal. A duty ratio of the first output signal and a duty ratio of the second output signal are different from a duty ratio of the first input signal and a duty ratio of the second input signal, respectively.Type: GrantFiled: May 5, 2020Date of Patent: December 28, 2021Assignee: KIOXIA CORPORATIONInventors: Yasuhiro Hirashima, Masaru Koyanagi, Mikihiko Ito, Kei Shiraishi, Fumiya Watanabe
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Publication number: 20210295930Abstract: According to one embodiment, in a semiconductor integrated circuit, an input circuit has an input and an output stage electrically connected to the input stage via a first node and a second node. The input stage includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first time constant adjusting circuit and a second time constant adjusting circuit. The first transistor has a gate that receives an input signal. The second transistor has a gate that receives a reference signal. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The first time constant adjusting circuit is electrically connected between a gate of the third transistor and the first node. The second time constant adjusting circuit is electrically connected between a gate of the fourth transistor and the second node.Type: ApplicationFiled: December 11, 2020Publication date: September 23, 2021Applicant: Kioxia CorporationInventors: Fumiya WATANABE, Masaru KOYANAGI, Yutaka SHIMIZU, Yasuhiro HIRASHIMA, Kei SHIRAISHI, Mikihiko ITO
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Patent number: 11121710Abstract: A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.Type: GrantFiled: August 24, 2020Date of Patent: September 14, 2021Assignee: KIOXIA CORPORATIONInventors: Yasuhiro Hirashima, Masaru Koyanagi, Yutaka Takayama
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Patent number: 11087852Abstract: A semiconductor storage device includes a first chip and a second chip. In response to a first command that is received on a first terminal of the first chip and a second terminal of the second chip that are connected to a command signal line, the first chip and the second chip execute in parallel a first correction process of correcting a duty cycle of a first output signal generated by the first chip and a second correction process of correcting a duty cycle of a second output signal generated by the second chip, respectively, according a common toggle signal.Type: GrantFiled: August 30, 2019Date of Patent: August 10, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yumi Takada, Yasuhiro Hirashima, Kenta Shibasaki, Yousuke Hagiwara
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Publication number: 20200389170Abstract: A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.Type: ApplicationFiled: August 24, 2020Publication date: December 10, 2020Inventors: Yasuhiro HIRASHIMA, Masaru KOYANAGI, Yutaka TAKAYAMA
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Patent number: 10847232Abstract: A semiconductor memory device includes a differential waveform shaping circuit including first and waveform shaping circuits connected in parallel. The first waveform shaping circuit has a first inverting amplifier, and two inverters connected in series. The first inverting amplifier inverts and differentially amplifies an input signal having a rectangular waveform. Then, the output of the first inverting amplifier is passed through the two inverters. The second waveform shaping circuit has a first inverter, a second inverting amplifier, and a second inverter connected in series. The second inverting amplifier inverts and differentially amplifies the output signal from the first invertor, and the second inverter inverts the output signal from the second inverting amplifier. The differential waveform shaping circuit generates an output signal by averaging the output signal from the first waveform shaping circuit and the output signal from the second waveform shaping circuit.Type: GrantFiled: August 29, 2019Date of Patent: November 24, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kei Shiraishi, Masaru Koyanagi, Mikihiko Ito, Yumi Takada, Yasuhiro Hirashima, Satoshi Inoue, Kensuke Yamamoto, Shouichi Ozaki, Taichi Wakui, Fumiya Watanabe
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Patent number: 10784866Abstract: A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.Type: GrantFiled: September 13, 2019Date of Patent: September 22, 2020Assignee: Toshiba Memory CorporationInventors: Yasuhiro Hirashima, Masaru Koyanagi, Yutaka Takayama
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Patent number: RE49783Abstract: A memory device includes a nonvolatile semiconductor memory cell array, a plurality of terminals through which control signals are received to control the memory device, an on-die termination circuit connected to at least one of the terminals and having a variable resistor, and a control circuit. The control circuit is configured to enable the on-die termination circuit in response to an enabling signal to enable the on-die termination circuit, with a resistance of the variable registor resistor at different values depending on whether a control signal is asserted or deasserted when the enabling signal is received.Type: GrantFiled: October 16, 2019Date of Patent: January 2, 2024Assignee: Kioxia CorporationInventors: Yasuhiro Hirashima, Masaru Koyanagi