Abstract: A semiconductor ROM includes a plurality of word lines disposed in parallel and has a plurality of units which each includes: a first main bit line and a second main bit line which cross the word lines; first, second, third, and fourth, sub-bit lines disposed substantially in parallel to the first and second main bit lines, and each of which has a first end and a second end; four memory cell columns, each including a plurality of memory cells connected in parallel between respective adjacent two of the sub-bit lines; and a plurality of bank selecting switches for selecting one of the four memory cell columns. First ends of the first sub-bit line and the third sub-bit line are connected to the first main bit line, and the second ends of the second sub-bit line and the fourth sub-bit line are connected to the second main bit line.

Abstract: A semiconductor memory device such as a ROM is provided with a word line test circuit and a word line drive circuit. The word line test circuit outputs a high level signal when a test signal is applied and a low level signal when the test signal is not applied. The word line drive circuit drives the respective word lines in the memory cell array, and is connected to the output of the word line test circuit, so that when driving one group of word lines (either the odd-numbered word lines or the even-numbered word lines), a high level signal is applied to the one group of word lines, and when not driving the one group of word lines, a low level signal is applied to the one group of word lines.

Abstract: A semiconductor read only memory of this invention includes a plurality of word lines disposed in parallel. The read only memory has a plurality of units.

Abstract: In a semiconductor memory device, two sense amplifiers are provided on one output signal line for reading data stored in a memory cell. The sense amplifiers are connected in parallel to each other. A control signal generation circuit generates a control signal so that one of the sense amplifiers which has a greater drive capability is activated during a predetermined time period after an address from which data are to be read out is changed, and that the sense amplifier having a smaller drive capability is activated during a time period other than the predetermined time period.

Abstract: A read-only memory includes columns of memory cell arrays, a plurality of banks formed by dividing each column of the memory cell arrays along the columns, sub-bit lines disposed between adjacent banks situated along the rows and connected to a transistor of each memory cell, and main-bit lines disposed between every two other columns of the memory cell arrays and extending along the columns, wherein the sub-bit lines are divided into sets of three sub-bit lines connected to a pair of adjacent banks situated along the rows, and one end of each center sub-bit line being connected to a first main-bit line through a first selector transistor, the first main-bit line passing through one side of the set to which the center bit-line belongs, and the other end of the sub-bit line being connected to a second main-bit line through a second selector transistor, the second main-bit line passing through the other side of the set to which the center sub-bit line belongs, the two outer sub-bit lines being directly connecte

Abstract: A semiconductor read only memory with hierarchical bit lines in which a resistance against a discharge current is constant irrespective of the position of a memory cell from which information is to be read is disclosed. A bank selecting MOSFET is connected to one end portion of a sub-bit line. Another bank selecting MOSFET is connected to the other end portion of the adjacent sub-bit line. Bank selecting MOSFETs are connected in the same alternate manner as described above. Therefore, since the resistance on bit lines against the read-out current is constant, a larger read-out current can be used especially when diffusion bit lines are used, whereby the semiconductor read only memory of the invention can achieve a high-speed read operation.

Abstract: A sense amplifier detects if a logic state of a detected memory cell transistor is "1" or "0" via a data line connected to the detected memory cell transistor. The sense amplifier includes a first dummy memory cell transistor which has characteristics identical to the "1" logic state characteristics of the detected memory cell transistor, a second dummy memory cell transistor which has characteristics identical to the "0" logic state characteristics of the detected memory cell transistor, and a differential amplifier circuit. The differential amplifier circuit receives signals from the data line and first and second reference lines respectively connected to the first and second dummy memory cell transistors, as a differential input, and outputs either a high or a low level according to the logic state of the detected memory cell based on the potential of the first or second reference line, the potential selected being that which differs from the potential of the data line.