Patents by Inventor Yasuhiro Ishizuka
Yasuhiro Ishizuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6902860Abstract: The present invention includes a two-layer imageable element, including: a substrate, a top layer including a first thermally imageable composition including (a) a first thermally sensitive supramolecular polymer or (b) a thermally imageable composition free of the first thermally sensitive supramolecular polymer; and disposed between the substrate and the top layer, a bottom layer including a second thermally imageable composition, which includes a second thermally sensitive supramolecular polymer. The present invention also includes a method of producing the imaged element.Type: GrantFiled: December 28, 2001Date of Patent: June 7, 2005Assignee: Kodak Polychrome Graphics LLCInventors: Yasuhiro Asawa, Yasuhiro Ishizuka, Eiji Hayakawa, S. Peter Pappas
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Patent number: 6829193Abstract: A power supply control circuit for use in a semiconductor storage device is provided. The power supply control circuit comprises a first power supply circuit connected to all subarrays of the semiconductor storage device, for supplying power to all the subarrays, an operation mode determination circuit for determining an operation mode in which the semiconductor storage device is placed and for generating a first block selection signal based on address information applied thereto according to the determined operation mode, a row control circuit disposed for each of all the subarrays, for generating a second block selection signal based on the first block selection signal according to the determined operation mode, and a second power supply circuit disposed for each of all the subarrays, for supplying power to a corresponding one of all the subarrays according to the second block selection signal from a corresponding row control circuit.Type: GrantFiled: June 5, 2002Date of Patent: December 7, 2004Assignees: Renesas Technology Corp., Mitsubishi Electric Engineering Company LimitedInventor: Yasuhiro Ishizuka
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Patent number: 6824947Abstract: Photosensitive compositions comprising a phenol resin having a urea bond in the main chain, planographic printing plate precursors containing the photosensitive compositions, and methods for preparing planographic printing plates using the planographic printing plate precursors are disclosed. Planographic printing plates that exhibit good durability, good exposure visual image property, and good solvent resistance; particularly superior resistance to washing oil used in UV ink printing; and superior baking property are produced.Type: GrantFiled: February 19, 2003Date of Patent: November 30, 2004Assignee: Kodak Polychrome Graphics, LLCInventors: Yasuhiro Ishizuka, Yasuhiko Kojima
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Publication number: 20030224281Abstract: Photosensitive compositions comprising a phenol resin having a urea bond in the main chain, planographic printing plate precursors containing the photosensitive compositions, and methods for preparing planographic printing plates using the planographic printing plate precursors are disclosed. Planographic printing plates that exhibit good durability, good exposure visual image property, and good solvent resistance; particularly superior resistance to washing oil used in UV ink printing; and superior baking property are produced.Type: ApplicationFiled: February 19, 2003Publication date: December 4, 2003Inventors: Yasuhiro Ishizuka, Yasuhiko Kojima
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Publication number: 20030011313Abstract: A power supply control circuit for use in a semiconductor storage device is provided. The power supply control circuit comprises a first power supply circuit connected to all subarrays of the semiconductor storage device, for supplying power to all the subarrays, an operation mode determination circuit for determining an operation mode in which the semiconductor storage device is placed and for generating a first block selection signal based on address information applied thereto according to the determined operation mode, a row control circuit disposed for each of all the subarrays, for generating a second block selection signal based on the first block selection signal according to the determined operation mode, and a second power supply circuit disposed for each of all the subarrays, for supplying power to a corresponding one of all the subarrays according to the second block selection signal from a corresponding row control circuit.Type: ApplicationFiled: June 5, 2002Publication date: January 16, 2003Inventor: Yasuhiro Ishizuka
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Publication number: 20020160299Abstract: The present invention includes a two-layer imageable element, including: a substrate, a top layer including a first thermally imageable composition including (a) a first thermally sensitive supramolecular polymer or (b) a thermally imageable composition free of the first thermally sensitive supramolecular polymer; and disposed between the substrate and the top layer, a bottom layer including a second thermally imageable composition, which includes a second thermally sensitive supramolecular polymer. The present invention also includes a method of producing the imaged element.Type: ApplicationFiled: December 28, 2001Publication date: October 31, 2002Applicant: Kodak Polychrome Graphics, L.L.C.Inventors: Yasuhiro Asawa, Yasuhiro Ishizuka, Eiji Hayakawa, S. Peter Pappas
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Patent number: 6418075Abstract: A semiconductor integrated circuit in which a logic and a memory are merged, includes a voltage generation unit for generating two or more internal power supply voltages based on two or more external power supply voltages supplied from outside the voltage generation unit with different timings and for furnishing the plurality of internal power supply voltages to the memory. The voltage generation unit includes a standby unit with a small current-feed ability that is always activated, for generating the plurality of internal power supply voltages, and an active unit with a large current-feed ability that is activated as needed, for generating the plurality of internal power supply voltages. An activation control unit prevents the active unit from being activated until all of the plurality of external power supply voltages rise.Type: GrantFiled: January 16, 2001Date of Patent: July 9, 2002Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Company LimitedInventors: Hiroki Shimano, Kazutami Arimoto, Yasuhiro Ishizuka, Seizou Furubeppu, Hiroki Sugano
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Patent number: 6356484Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.Type: GrantFiled: January 10, 2000Date of Patent: March 12, 2002Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Co., Ltd.Inventors: Katsumi Dosaka, Masaki Kumanoya, Yasuhiro Konishi, Katsumitsu Himukashi, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe, Yasuhiro Ishizuka, Tsukasa Saika
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Publication number: 20020008547Abstract: A semiconductor integrated circuit in which a logic and a memory are merged, includes a voltage generation unit for generating two or more internal power supply voltages based on two or more external power supply voltages supplied from outside the voltage generation unit with different timings and for furnishing the plurality of internal power supply voltages to the memory. The voltage generation unit includes a standby unit with a small current-feed ability that is always activated, for generating the plurality of internal power supply voltages, and an active unit with a large current-feed ability that is activated as needed, for generating the plurality of internal power supply voltages. An activation control unit prevents the active unit from being activated until all of the plurality of external power supply voltages rise.Type: ApplicationFiled: January 16, 2001Publication date: January 24, 2002Inventors: Hiroki Shimano, Kazutami Arimoto, Yasuhiro Ishizuka, Seizou Furubeppu, Hiroki Sugano
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Publication number: 20010040827Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRUM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.Type: ApplicationFiled: January 10, 2000Publication date: November 15, 2001Inventors: KATSUMI DOSAKA, MASAKI KUMANOYA, YASUHIRO KONISHI, KATSUMITSU HIMUKASHI, KOUJI HAYANO, AKIRA YAMAZAKI, HISASHI IWAMOTO, HIDEAKI ABE, YASUHIRO ISHIZUKA, TSUKASA SAIKI
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Patent number: 6026029Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.Type: GrantFiled: May 29, 1997Date of Patent: February 15, 2000Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Co., Ltd.Inventors: Katsumi Dosaka, Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe, Yasuhiro Konishi, Katsumitsu Himukashi, Yasuhiro Ishizuka, Tsukasa Saiki
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Patent number: 5848004Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.Type: GrantFiled: March 28, 1996Date of Patent: December 8, 1998Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Co., Ltd.Inventors: Katsumi Dosaka, Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe, Yasuhiro Konishi, Katsumitsu Himukashi, Yasuhiro Ishizuka, Tsukasa Saiki
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Patent number: 5731127Abstract: A photosensitive composition which comprises a resin (A) having urea bonds in its side chains and a photosensitive compound (B), wherein the resin (A) contains at least one resin selected from the group consisting of a vinyl polymer resin and a condensation polymer resin, provides a coating layer with excellent resistance to solvents and abrasion. The photosensitive composition is suitable for use in the production of planographic printing plates, integrated circuits (IC) or photomasks. A photosensitive planographic printing plate produced usig the photosensitive composition has superior press-life.Type: GrantFiled: April 9, 1996Date of Patent: March 24, 1998Assignee: Dainippon Ink and Chemicals, Inc.Inventors: Yasuhiro Ishizuka, Maru Aburano, Eiji Hayakawa, Koji Oe
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Patent number: 5652723Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.Type: GrantFiled: April 15, 1992Date of Patent: July 29, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Katsumi Dosaka, Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe, Yasuhiro Konishi, Katsumitsu Himukashi, Yasuhiro Ishizuka, Tsukasa Saiki
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Patent number: 5650968Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.Type: GrantFiled: May 21, 1996Date of Patent: July 22, 1997Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Co., Ltd.Inventors: Katsumi Dosaka, Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe, Yasuhiro Konishi, Katsumitsu Himukashi, Yasuhiro Ishizuka, Tsukasa Saiki
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Patent number: 5629895Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.Type: GrantFiled: April 30, 1996Date of Patent: May 13, 1997Assignees: Mitsubishi Electric Engineering Co., Ltd., Mitsubishi Denki Kabushiki KaishaInventors: Katsumi Dosaka, Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe, Yasuhiro Konishi, Katsumitsu Himukashi, Yasuhiro Ishizuka, Tsukasa Saiki
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Patent number: 5623454Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.Type: GrantFiled: February 9, 1996Date of Patent: April 22, 1997Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Co., Ltd.Inventors: Katsumi Dosaka, Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe, Yasuhiro Konishi, Katsumitsu Himukashi, Yasuhiro Ishizuka, Tsukasa Saiki
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Patent number: 5583813Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.Type: GrantFiled: June 5, 1995Date of Patent: December 10, 1996Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Co., Ltd.Inventors: Katsumi Dosaka, Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe, Yasuhiro Konishi, Katsumitsu Himukashi, Yasuhiro Ishizuka, Tsukasa Saiki
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Patent number: 5559750Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.Type: GrantFiled: June 5, 1995Date of Patent: September 24, 1996Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Co., Ltd.Inventors: Katsumi Dosaka, Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe, Yasuhiro Konishi, Katsumitsu Himukashi, Yasuhiro Ishizuka, Tsukasa Saiki
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Patent number: 5544121Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.Type: GrantFiled: June 5, 1995Date of Patent: August 6, 1996Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Co., Ltd.Inventors: Katsumi Dosaka, Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe, Yasuhiro Konishi, Katsumitsu Himukashi, Yasuhiro Ishizuka, Tsukasa Saiki