Abstract: In a battery pack (1),a current loop between the positive and negative electrode plates of an electrode assembly passes points P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13 and P14 in this order. A line that connects P2 to P3 intersects a line that connects P11 to P12 in the part where the loop passes a sealing plate (12), which is arranged on the top of a battery unit (10). The loop can be divided into loop parts B1 and B2. The part B1 is formed on the exterior side of the battery unit, and extends from the intersection A through a circuit board (20) back to the intersection A. The part B2 is formed on the interior side of the battery unit relative to the intersection A. The current flows counterclockwise and clockwise in the parts B1 and B2, respectively.

Abstract: In a battery pack (1), a current loop between the positive and negative electrode plates of an electrode assembly passes points P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13 and P14 in this order. A line that connects P2 to P3 intersects a line that connects P11 to P12 in the part where the loop passes a sealing plate (12), which is arranged on the top of a battery unit (10). The loop can be divided into loop parts B1 and B2. The part B1 is formed on the exterior side of the battery unit, and extends from the intersection A through a circuit board (20) back to the intersection A. The part B2 is formed on the interior side of the battery unit relative to the intersection A. The current flows counterclockwise and clockwise in the parts B1 and B2, respectively.

Abstract: In a wiring substrate, a wiring layer includes a pair of differential transmission lines. A conductive layer is provided on one side of the wiring layer. The conductive layer is grounded. An insulating layer is provided between the wiring layer and the conductive layer. The conductive layer includes a region, formed by an electrically continuous conductor, within a filter region. At least part of the conductor is turned around in the region. Seen from a stacking direction, the pair of differential transmission lines intersects with at least two strip portions disposed counter to each other because of the turning-around of the electrically continuous conductor.

Abstract: A signal current wiring line is configured to carry a signal current from a first circuit block to a second circuit block. A return current wiring line is configured to carry a return current from the second circuit block to the first circuit block. The signal current wiring line and the return current wiring line are stacked with an offset in the width direction so as to form a region between the surface of the casing on the second wiring line side and the signal current wiring line where the signal current wiring line faces the surface of the casing on the second wiring line side without the return current wiring line intervening between them.

Abstract: A first field effect transistor receives an unbalanced signal from an input terminal at the gate thereof, and outputs a balanced signal from the drain thereof. A second field effect transistor has the gate thereof connected to the drain of the first field effect transistor and outputs a balanced signal from the drain thereof. The sources of the first field effect transistor and the second field effect transistor are connected to the drain of a third field effect transistor serving as a current source. The drain of the second field effect transistor is connected to the gate of the first field effect transistor via a first resistor. A first output terminal is connected between the drain of the first field effect transistor and the first resistor, and a second output terminal is connected between the drain of the second field effect transistor and a second resistor.

Abstract: A first field effect transistor receives an unbalanced signal from an input terminal at the gate thereof, and outputs a balanced signal from the drain thereof. A second field effect transistor has the gate thereof connected to the drain of the first field effect transistor and outputs a balanced signal from the drain thereof. The sources of the first field effect transistor and the second field effect transistor are connected to the drain of a third field effect transistor serving as a current source. The drain of the second field effect transistor is connected to the gate of the first field effect transistor via a first resistor. A first output terminal is connected between the drain of the first field effect transistor and the first resistor, and a second output terminal is connected between the drain of the second field effect transistor and a second resistor.

Abstract: A first circuit which is constituted by a thin film resistor is connected between the collector of a transistor and a power supply terminal, and a second circuit which is constituted by a semiconductor resistor is connected between the emitter of the transistor and a grounding terminal. The film thickness of a thin film resistor is set to not more than its skin depth at a frequency to be compensated for.

Abstract: A communication apparatus includes, as a plurality of communication functions, an amplifier for amplifying a received signal or a transmitting signal, a balun for converting an unbalanced signal to a balanced signal or converting a balanced signal to an unbalanced signal and a mixer for converting a frequency. A gain reducing unit for reducing a gain of a specific frequency band is installed in at least one of the plurality of communication functions. A band rejection filter, for example, serves as a gain reducing unit and is disposed between a pair of transistors. A plurality of band rejection filters may be so arranged as to be distributed to the plurality of communication functions.

Abstract: A first circuit which is constituted by a thin film resistor is connected between the collector of a transistor and a power supply terminal, and a second circuit which is constituted by a semiconductor resistor is connected between the emitter of the transistor and a grounding terminal. The film thickness of a thin film resistor is set to not more than its skin depth at a frequency to be compensated for.