Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Abstract: A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.

Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Abstract: A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Each chip is bonded with an associated lead frame and each lead frame is disposed as plural lead frame conductors contacting mutually lead frame conductors associated with similarly function bonding pads, i.e. external terminals of the chips, of the other one of the pair of chips. Ones or plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal.

Abstract: An output circuit is provided which includes a first switch coupled between a first power supply terminal and an output terminal, a second switch coupled between the first power supply terminal and the output terminal, an arrangement to set the output terminal at a high impedance state, and a first variable delay coupled to a first input terminal for turning on the first switch and the second switch with different timing from each other and for turning off the first switch and the second switch simultaneously. In addition, the output circuit includes a third switch coupled between the output terminal and a second power supply terminal, a fourth switch coupled between the output terminal and the second power supply terminal, and a second variable delay coupled to a second input terminal for turning on the third switch and the fourth switch with different timing from each other and for turning off the third switch and the fourth switch simultaneously.

Abstract: A semiconductor integrated circuit memory structure is provided which uses macro-cellulated circuit blocks that can permit a very large storage capability (for example, on the order of 64 Mbits in a DRAM) on a single chip. To achieve, this, a plurality of macro-cellulated memory blocks can be provided, with each of the memory blocks including a memory array as well as additional circuitry such as address selection circuits and input/output circuits. Other peripheral circuits are provided on the chip which are common to the plurality of macro-cell memory blocks. The macro-cell memory blocks themselves can be formed in an array so that their combined storage capacity will form the large overall storage capacity of the chip. The combination of the macro-cell memory blocks and the common peripheral circuitry for controlling the memory blocks permits a faster and more efficient refreshing operation for a DRAM. This is enhanced by a LOC (Lead On Chip) arrangement used in conjunction with the memory blocks.

Abstract: A memory device is provided including a plurality of memory arrays and peripheral circuits. For example, in a dynamic RAM the peripheral circuitry will include row address decoders, column address decoders, sense amplifiers and main amplifiers disposed in such a manner as to correspond to the memory arrays, respectively. The desired row address decoders, column address decoders, sense amplifiers and main amplifiers are selectively operated in accordance with a common array selection signal generated on the basis of at least part of row address signals. Accordingly, only the row address decoders, column address decoders, sense amplifiers and main amplifiers corresponding to the memory array containing the designated memory cells are operated selectively in accordance with the common array selection signal. It is thus possible to reduce power consumption of the dynamic RAM and to simplify the structure of the peripheral circuits and wirings.

Abstract: A semiconductor memory wherein an operating mode is selectively set by effecting bonding with respect to predetermined pads provided on a common semiconductor substrate in a predetermined combination or by cutting off predetermined fuse means provided on the common semiconductor substrate in a predetermined combination and a bit pattern is selectively set by changing a part of a photomask applied to the common semiconductor substrate.

Abstract: A semiconductor memory wherein an operating mode is selectively set by effecting bonding with respect to predetermined pads provided on a common semiconductor substrate in a predetermined combination or by cutting off predetermined fuse means provided on the common semiconductor substrate in a predetermined combination and a bit pattern is selectively set by changing a part of a photomask applied to the common semiconductor substrate.

Abstract: A memory device is provided including a plurality of memory arrays and peripheral circuits. For example, in a dynamic RAM the peripheral circuitry will include row address decoders, column address decoders, sense amplifiers and main amplifiers disposed in such a manner as to correspond to the memory arrays, respectively. The desired row address decoders, column address decoders, sense amplifiers and main amplifiers are selectively operated in accordance with a common array selection signal generated on the basis of at least part of row address signals. Accordingly, only the row address decoders, column address decoders, sense amplifiers and main amplifiers corresponding to the memory array containing the designated memory cells are operated selectively in accordance with the common array selection signal. It is thus possible to reduce power consumption of the dynamic RAM and to simplify the structure of the peripheral circuits and wirings.