Abstract: A transmitter circuit, which transmits data by using an impulse, has a variable delay circuit and a logic circuit. The variable delay circuit takes a clock as an input, and delays the clock in accordance with the data. The logic circuit takes the clock and an output of the variable delay circuit as inputs, and outputs an impulse by performing a logic operation between the clock and the output of the variable delay circuit.

Abstract: A radio communication apparatus includes a baseband signal generator to generate digital data; a clock generator to generate 2N pulse signals corresponding to the digital data; a selector to select one of the 2N pulse signals; and a short pulse generator to reduce a pulse width of the signal selected by the selector, wherein the 2N pulse signals include a whole-period non-transmission pulse, a whole-period transmission pulse, and 2N-2 partial-period transmission pulses, when the partial-period transmission pulse is selected, a band pass filter outputs a signal that lasts for part of a period having a 1-symbol length, when the whole-period non-transmission pulse is selected, the band pass filter outputs a signal attenuated by offsetting signals corresponding to the whole-period non-transmission pulse, and when the whole-period transmission pulse is selected, the band pass filter outputs a signal that lasts for a whole of the period having the 1-symbol length.

Abstract: A communication device includes an oscillator to generate an oscillation signal; a harmonic generator to generate a higher harmonic wave from the oscillation signal; a first filter to take out a first high frequency signal; a second filter to take out a second high frequency signal; a down conversion mixer to use the second high frequency signal to perform down conversion of a signal obtained by receiving a reflected signal of the first high frequency signal; a hybrid coupler to generate a first intermediate frequency signal and a second intermediate frequency signal, which are orthogonal with each other; a first mixer to take out a first baseband signal by mixing an output from the down conversion mixer with the first intermediate frequency signal; and a second mixer to take out a second baseband signal by mixing an output from the down conversion mixer with the first intermediate frequency signal.

Abstract: An impulse radio communication device includes a short pulse generator configured to change a shape of an impulse to be output; a bandpass filter configured to receive the impulse and output the impulse as a wave packet; an amplifier configured to amplify an output from the bandpass filter; and an antenna configured to output the wave packet, output from the amplifier, as a wireless signal, the short pulse generator includes a control section configured to change the shape of the impulse to be output, in response to an environmental condition of a transmission path for wireless communication.

Abstract: A transmission device including a pulse generating section configured to generate a plurality of pulses using a signal of data and a signal obtained by delaying the signal of data, and to adjust the pulse width such that each of the plurality of pulses has a pulse width conforming to a sequence of the data; a band-pass filter filtering the plurality of pulses; and a transmission amplifier amplifying the filtered plurality of pulses and outputting the filtered plurality of pulses as a transmission signal.

Abstract: The impulse generator comprises a nonlinear transmission line capable of obtaining an impulse with a small half value width and a large amplitude, in which a plurality of transmission line units having a unit line unit and a diode are connected in series, a pulse generator connected to the transmission terminal of the nonlinear transmission line, and a bias-dependent element connected to the reception terminal of the nonlinear line, wherein the anode of the diode of the transmission line unit is connected to the transmission line and the cathode is connected to the ground, and one end of the bias-dependent element is connected to the reception terminal of the transmission line and the other end is biased to a negative potential.

Abstract: A radio transmission apparatus has a first duty adjustment circuit which changes a duty of a clock signal, a second duty adjustment circuit which changes the duty of the clock signal to a duty different from the duty of the clock signal changed by the first duty adjustment circuit, a first AND circuit which takes a logical product between a data signal and the clock signal having passed through the first duty adjustment circuit, and a second AND circuit which takes a logical product between an output signal of the first AND circuit and the clock signal having passed through inversion of the output of the second duty adjustment circuit to generate a pulse signal.

Abstract: A phase shifter circuit includes a plurality of first series circuits each comprised of a series connection of one capacitor and one resistor, a first circuit element including at least inductance connecting between a first end and a second end of a chain structure made by connecting the plurality of first series circuits in series, the first circuit element and the chain structure together constituting a first loop circuit, a plurality of second series circuits each comprised of a series connection of one capacitor and one resistor, a second circuit element including at least inductance connecting between a first end and a second end of a chain structure made by connecting the plurality of second series circuits in series, the second circuit element and the chain structure together constituting a second loop circuit, and a plurality of connection lines connecting between the first loop circuit and the second loop circuit.

Abstract: A radar device has a clock generator (131) generating a base clock; a transmitter (121 to 125) transmitting transmission pulses as gradually increasing a displacement amount with respect to each edge of the base clock; and a receiver (101 to 106) receiving reflected waves of the transmitted transmission pulses in synchronization with the edges of the base clock.

Abstract: A pulse transmission method for transmitting data by using pulse signals, each having a predetermined pulse width; defining a symbol time at least N times the predetermined pulse width, N being at least 2; defining a basic delay time calculated by dividing the predetermined pulse width by a predetermined integer; placing the pulse signals in the symbol time by delaying the pulse signals by an integral multiple of the basic delay time from start of the symbol time, the number of the pulse signals being k and 0?k?N being satisfied; and transmitting the pulse signals.

Abstract: A radar device has a clock generator (131) generating a base clock; a transmitter (121 to 125) transmitting transmission pulses as gradually increasing a displacement amount with respect to each edge of the base clock; and a receiver (101 to 106) receiving reflected waves of the transmitted transmission pulses in synchronization with the edges of the base clock.

Abstract: A frequency dividing circuit has a master circuit and a slave circuit, and a load section in at least either one of the master and slave circuits is constructed to provide an impedance that decreases with increasing frequency.

Abstract: The impulse generator comprises a nonlinear transmission line capable of obtaining an impulse with a small half value width and a large amplitude, in which a plurality of transmission line units having a unit line unit and a diode are connected in series, a pulse generator connected to the transmission terminal of the nonlinear transmission line, and a bias-dependent element connected to the reception terminal of the nonlinear line, wherein the anode of the diode of the transmission line unit is connected to the transmission line and the cathode is connected to the ground, and one end of the bias-dependent element is connected to the reception terminal of the transmission line and the other end is biased to a negative potential.

Abstract: A transmitter circuit, which transmits data by using an impulse, has a variable delay circuit and a logic circuit. The variable delay circuit takes a clock as an input, and delays the clock in accordance with the data. The logic circuit takes the clock and an output of the variable delay circuit as inputs, and outputs an impulse by performing a logic operation between the clock and the output of the variable delay circuit.

Abstract: A phase shifter circuit includes a plurality of first series circuits each comprised of a series connection of one capacitor and one resistor, a first circuit element including at least inductance connecting between a first end and a second end of a chain structure made by connecting the plurality of first series circuits in series, the first circuit element and the chain structure together constituting a first loop circuit, a plurality of second series circuits each comprised of a series connection of one capacitor and one resistor, a second circuit element including at least inductance connecting between a first end and a second end of a chain structure made by connecting the plurality of second series circuits in series, the second circuit element and the chain structure together constituting a second loop circuit, and a plurality of connection lines connecting between the first loop circuit and the second loop circuit.

Abstract: A sample-hold circuit, which reduces droop and feed through and is suitable for high-speed operation while maintaining a wider freedom of design parameters, comprising a preamplifier to which an input analog signal is applied, a core section which outputs a voltage corresponding to the variation of an output from the preamplifier during the sampling period and holds the voltage corresponding to the output from the preamplifier during the hold period initiated by a transition of a clock signal, and a current switching circuit which is connected to the output pin of the preamplifier and enables the current flowing into the first transistor within the preamplifier during the sampling period to flow into another second transistor to apply a constant potential as an input to the core section.

Abstract: A sample-hold circuit, which reduces droop and feed through and is suitable for high-speed operation while maintaining a wider freedom of design parameters, comprising a preamplifier to which an input analog signal is applied, a core section which outputs a voltage corresponding to the variation of an output from the preamplifier during the sampling period and holds the voltage corresponding to the output from the preamplifier during the hold period initiated by a transition of a clock signal, and a current switching circuit which is connected to the output pin of the preamplifier and enables the current flowing into the first transistor within the preamplifier during the sampling period to flow into another second transistor to apply a constant potential as an input to the core section.

Abstract: A semiconductor memory device including a plurality of bit lines and a plurality of word lines which intersect to form a matrix of cross points. A respective memory cell is disposed at each cross point and corresponds to the respective word line and respective bit line intersecting at the respective cross point. Each memory cell includes a transfer gate having a first current terminal connected to the corresponding bit line and a control terminal connected to the corresponding word line. Each memory cell also includes a pair of serially connected negative differential resistance memory elements having an interconnection node therebetween. The interconnection node is connected to the second current terminal of the transfer gate.