Abstract: A method for manufacturing a semiconductor device according to the present invention comprises: forming a semiconductor circuit including a first transistor with a first threshold voltage and a first drain-source current; applying a stress voltage to the first transistor to make at least one of a change from the first threshold voltage a second threshold voltage and a change from the first drain-source current to a second drain-source current; and shipping the semiconductor circuit while the first transistor is presenting one of the second threshold voltage and the second drain-source current.

Abstract: Disclosed is a semiconductor memory device equipped with an on-chip comparison and latching function, including a latch circuit which receives a comparison result signal, output from a compare circuit receiving read data signals from plural data bus signals and an input data signal from outside and comparing whether or not the signals coincide with each other, to output the result of latching of the fail information based on a control signal. The latch circuit latches and outputs the fail information of a preset number bit output from the compare circuit during the time when a control signal for latching and outputting the fail information is in active state.

Abstract: A second roll call test mode is added in addition to a first roll call test mode for checking use/nonuse of a redundancy circuit. A semiconductor memory device is capable of confirming program states of an enable fuse and each address fuse by providing with a logic circuit which blocks program information of the enable fuse by using a second test mode signal.

Abstract: Disclosed is a semiconductor memory device equipped with an on-chip comparison and latching function, including a latch circuit which receives a comparison result signal, output from a compare circuit receiving read data signals from plural data bus signals and an input data signal from outside and comparing whether or not the signals coincide with each other, to output the result of latching of the fail information based on a control signal. The latch circuit latches and outputs the fail information of a preset number bit output from the compare circuit during the time when a control signal for latching and outputting the fail information is in active state.

Abstract: A redundancy control circuit includes a redundancy decoder and a decoder killer circuit. The redundancy decoder includes a plurality of fuse circuits corresponding to a plurality of determination signals which are previously activated, and each of the plurality of fuse circuits contains a plurality of fuse sections each containing a fuse. The decoder killer circuit generates a killer signal when at least one of the plurality of determination signals is active, and the killer signal is outputted to an external unit in a first check mode. One of the plurality of fuse circuits is selected and determination signals corresponding to non-selected fuse circuits are inactivated. A specific fuse section of the selected fuse circuit inactivates the determination signal to provide indication of whether the fuse section is cut.

Abstract: A redundancy control circuit includes a redundancy decoder and a decoder killer circuit. The redundancy decoder includes a plurality of fuse circuits corresponding to a plurality of determination signals which are previously activated, and each of the plurality of fuse circuits contains a plurality of fuse sections, and each of the fuse sections contains a fuse. The decoder killer circuit generates a killer signal when at least one of the plurality of determination signals is active, and the killer signal is outputted to an external unit in a first check mode. One of the plurality of fuse circuits is selected based on a first control signal and a first address bits of a first address in the first check mode, and the determination signals corresponding to the non-selected fuse circuits are inactivated.

Abstract: A method is disclosed for checking the state of a capacitor fuse in which the voltage that is applied to the capacitor fuse is made the same level as voltage that is applied to memory cells. When detecting the occurrence of cutting of a capacitor fuse, voltage HVCCF (0.7 V), which is a voltage that is half the voltage of the power supply VINTS (1.4 V) for driving a sense amplifier, is used to charge the capacitor fuse, and the difference in potential between the voltage that has accumulated in the capacitor fuse and a voltage (0.5 V) that is lower than HVCCF is amplified by a sense amplifier and then latched by a latch circuit unit. Voltage HVCCF (0.7 V) that is applied across the two electrodes of the capacitor fuse is a voltage of the same level as the voltage that is applied to normal memory cells, and the reliability of the semiconductor memory device is therefore improved.

Abstract: A method is disclosed for checking the state of a capacitor fuse in which the voltage that is applied to the capacitor fuse is made the same level as voltage that is applied to memory cells. When detecting the occurrence of cutting of a capacitor fuse, voltage HVCCF (0.7 V), which is a voltage that is half the voltage of the power supply VINTS (1.4 V) for driving a sense amplifier, is used to charge the capacitor fuse, and the difference in potential between the voltage that has accumulated in the capacitor fuse and a voltage (0.5 V) that is lower than HVCCF is amplified by a sense amplifier and then latched by a latch circuit unit. Voltage HVCCF (0.7 V) that is applied across the two electrodes of the capacitor fuse is a voltage of the same level as the voltage that is applied to normal memory cells, and the reliability of the semiconductor memory device is therefore improved.

Abstract: A semiconductor memory device having a refresh function to restore data stored in a memory cell, comprises a delay switching block for delaying a signal for deactivating a word line in a self-refresh operation as compared with the signal in a CBR refresh operation. The delay switching block comprises: a first signal path for allowing the signal for deactivating the word line to pass; a second signal path for delaying the signal for deactivating the word line by a predetermined time; and a path selecting block for selecting the first signal path in the CBR refresh operation, and for selecting the second signal path in the self-refresh operation.

Abstract: When a /RAS (/row address strobe) signal is input to a memory device, a control logic of the memory device issues an internal /RAS signal corresponding to the /RAS signal and then a row decoder drives a selected wordline in response to the internal /RAS signal. A predetermined time internal passes from the issuance of the internal /RAS signal to the drive of the selected wordline, depending upon a circuit layout of the memory device, skew and so forth. The predetermined time interval is utilized for a time of pre-booting at a booting circuit.

Abstract: When a /RAS (/row address strobe) signal is input to a memory device, a control logic of the memory device issues an internal /RAS signal corresponding to the /RAS signal and then a row decoder drives a selected wordline in response to the internal /RAS signal. A predetermined time internal passes from the issuance of the internal /RAS signal to the drive of the selected wordline, depending upon a circuit layout of the memory device, skew and so forth. The predetermined time interval is utilized for a time of pre-booting at a booting circuit.

Abstract: A semiconductor memory device having a refresh function to restore data stored in a memory cell, comprises a delay switching block for delaying a signal for deactivating a word line in a self-refresh operation as compared with the signal in a CBR refresh operation. The delay switching block comprises: a first signal path for allowing the signal for deactivating the word line to pass; a second signal path for delaying the signal for deactivating the word line by a predetermined time; and a path selecting block for selecting the first signal path in the CBR refresh operation, and for selecting the second signal path in the self-refresh operation.

Abstract: When a dynamic random access memory device is powered with an external power voltage, a first intermediate voltage generator produces an intermediate voltage from the external power voltage for supplying to the counter electrodes of the storage capacitors of memory cells and a precharge unit, and the first intermediate voltage generator is replaced with a second intermediate voltage generator after the internal power voltage becomes stable, wherein a switch transistor blocks the counter electrodes and the precharge unit from the second intermediate voltage generator during a test operation on bit lines, thereby effectively screening out defective products.

Abstract: An image sensing device that outputs a signal logarithmically proportional to the intensity of the incident light. The image sensing device makes use of a sub-threshold current flowing between the drain and source of a MOS transistor when the gate voltage is below the threshold voltage (above which the MOS transistor is nominally conductive and below which nominally non-conductive). Since the logarithmic conversion is done in the photosensing section of a solid-state image sensing device, the output from the device is already compressed and is easily handled by a small capacity CCD. Some output systems for the image sensing device of the present invention are also described.

Abstract: A focus detecting photoelectric device includes a plurality of photodiodes each formed by an amorphous silicon layer sandwiched between transparent and non-transparent electrodes. The photodiodes are provided in pairs and are aligned in an array and deposited on a glass plate such that the transparent electrode is directly mounted on the glass plate. The photodiodes in a pair are located closely adjacent to, but in a spaced relation with, each other and are electrically connected in series to each other. An image formed on the photodiodes in a pair effects the generation of photocurrent from the photodiodes such that the photocurrents from both photodiodes are approximately the same when the image is out of focus, and they vary from each other as the image becomes sharp.

Abstract: A distance measuring device includes light emitting diode for emitting light toward a subject to be photographed, and a pair of light receiving elements spaced by a predetermined base length from the light receiving diode. The light receiving elements are position side-by-side such that the boundary therebetween extends in a direction which is perpendicular to the direction of the base length so that an image formed by the light emitted to, and reflected from, the subject, will be formed on the light receiving elements in a bridged manner. The respective areas on the light receiving elements occupied by the image differ relative to the distance to the subject. A ratio between the signal levels obtained from the light receiving elements is calculated as a signal representing the distance to the subject.

Abstract: A photographic camera having an automatic rangefinder system wherein a light emitter projects a beam of light through a convergent lens to illuminate a target object. This beam of light is detected through another convergent lens by one of a group of photoresponsive elements forming a light receiver. Depending upon which photoresponsive element of the light receiver detects the reflected beam of light, the range of the target object to be photographed from the photographic camera is indicated. The light emitter and the light receiver are supported by a single support member in laterally offset relation to each other and the lens elements for converging the projected beam of light and the reflected beam of light, respectively, are integrally formed of a synthetic resin. The rangefinder elements are assembled into a rangefinder module.

Abstract: This invention is directed to a rangefinding system which includes a light beam source, a plurality of light receiving elements disposed to receive an image light spot reflected from a target object existing in any one of a group of distance zones in such manner that the image light spot is projected on one or more of the light receiving elements, the light receiving elements being adapted to produce a combination of outputs, the contents of which vary depending on the distance between the target object and the rangefinding system the invention also includes a logic circuit for producing signals indicating the distance zone in which the target object exists, the signal generated in response to the combination of outputs, so that the space occupied by the light receiving elements can be advantageously decreased and the precision of rangefinding can be improved.

Abstract: A photoelectric rangefinder for use in a photographic camera for automatically focusing an image of a target object on a predetermined image plane. The system utilizes an electro-optical spatial filter having at least two photoresponsive elements to find the difference in phase between output signals from the respective photoresponsive elements. A signal indicative of the difference in phase between the output signals from the photoresponsive elements is used to move a phototaking objective lens along its optical path to reposition the objective lens in search for a true focus setting. The objective lens is brought into proper focus when the signal indicative of the phase difference assumes a predetermined electric relation with an electric signal indicative of the position of the objective lens along its optical axis.

Abstract: A camera is equipped with a member bearing data to be photographed such as a date and the like and a data light focusing optical system for projecting the illuminated data from the data member at the front of the camera rearwardly with the object light toward the data photographing portion of the film. The data light focusing optical system is arranged so that the data light is directed to be incident on the data photographing portion of the film from a direction different from the incident direction of the object light. Provided in the front of the data photographing portion of the film is an object light incidence limiting member which is positioned parallel with the plane of the film and allows the transmission of the data light therethrough but interrupts the object light directed toward the data light focusing portion of the film.