Patents by Inventor Yasuhiro Sagesaka
Yasuhiro Sagesaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10784905Abstract: To provide a communication device that can suppress radio wave interference in communication using a plurality of frequency signals in a simply method, a communication device includes a first communication unit that communicates with a first external device by using a first frequency signal, a second communication unit that communicates with a second external device by using a second frequency signal, and a control unit that controls, when one of the first and second communication units transmits data to a corresponding one of the first and second external devices, the other of the first and second communication units not to receive data.Type: GrantFiled: June 20, 2019Date of Patent: September 22, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yasuhiro Sagesaka, Suguru Fujita
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Patent number: 10542379Abstract: An on-vehicle communication device has a communication unit which communicates with a roadside device, a roadside device position information storage unit which stores in advance first position information indicating a position of the roadside device, a vehicle position information acquisition unit which acquires second position information indicating a position of the vehicle, an approach decision unit which decides whether the vehicle approaches the roadside device on the basis of the first position information stored in the roadside device position information storage unit and the second position information that the vehicle position information acquisition unit acquires and a communication control unit which switches a state of the communication unit from a power-saving state to a non-power-saving state in a case where the approach decision unit decides that the vehicle approaches the roadside device.Type: GrantFiled: August 21, 2018Date of Patent: January 21, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Yasuhiro Sagesaka
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Publication number: 20200007172Abstract: To provide a communication device that can suppress radio wave interference in communication using a plurality of frequency signals in a simply method, a communication device includes a first communication unit that communicates with a first external device by using a first frequency signal, a second communication unit that communicates with a second external device by using a second frequency signal, and a control unit that controls, when one of the first and second communication units transmits data to a corresponding one of the first and second external devices, the other of the first and second communication units not to receive data.Type: ApplicationFiled: June 20, 2019Publication date: January 2, 2020Inventors: Yasuhiro SAGESAKA, Suguru FUJITA
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Patent number: 10374796Abstract: Provided is a high-speed and light-weighted authentication system that makes IP address filtering possible and does not impair real-time property even on a network including many and unspecific entities (communication devices). In a communication system that a plurality of communication devices are coupled together such that mutual communication is possible over the network, the communication devices communicate with a server under a secure environment, when authentication has been obtained from the server, random seeds of the same value and individual identifiers are issued to them, each communication device generates the IP address that includes a pseudorandom number and the identifier, and the communication devices establish communication between the communication devices that include the pseudorandom numbers that are mutually the same in their IP addresses.Type: GrantFiled: August 26, 2015Date of Patent: August 6, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Daisuke Oshida, Yoshiyuki Sato, Yasuhiro Sagesaka, Takeshi Itome
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Publication number: 20190164356Abstract: An object of the present invention is to reduce the number of errors generated in an in-vehicle communication device due to a communication failure between the in-vehicle communication device and an IC card. The in-vehicle communication device has a communication unit that performs a first communication with a roadside machine, an interface that performs a second communication with an IC card, a non-volatile memory, and a processing unit that executes a process of collecting a toll using the communication unit. The processing unit stores predetermined information stored in the IC card into the non-volatile memory, uses the information stored in the non-volatile memory when executing a process using the communication unit, and writes the information stored in the non-volatile memory into the IC card at, at least, either timing when the power supply of the in-vehicle communication device 1 is switched to on or off.Type: ApplicationFiled: September 11, 2018Publication date: May 30, 2019Inventors: Yasuhiro SAGESAKA, Shigeru FURUTA
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Publication number: 20190116462Abstract: An on-vehicle communication device has a communication unit which communicates with a roadside device, a roadside device position information storage unit which stores in advance first position information indicating a position of the roadside device, a vehicle position information acquisition unit which acquires second position information indicating a position of the vehicle, an approach decision unit which decides whether the vehicle approaches the roadside device on the basis of the first position information stored in the roadside device position information storage unit and the second position information that the vehicle position information acquisition unit acquires and a communication control unit which switches a state of the communication unit from a power-saving state to a non-power-saving state in a case where the approach decision unit decides that the vehicle approaches the roadside device.Type: ApplicationFiled: August 21, 2018Publication date: April 18, 2019Inventor: Yasuhiro SAGESAKA
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Publication number: 20170092126Abstract: There is provided a communication system including the first communication device (roadside unit), a second communication device, and a data processing device. The first communication device is capable of establishing broadcast-type first communication (V2X communication) with the first communication terminal (vehicle). The second communication device is capable of establishing unicast- or multicast-type second communication with a plurality of moving objects (pedestrians) other than the first communication terminal and acquiring position information about the moving objects (pedestrians). The data processing device permits the second communication device to acquire position information about the moving objects and allows the first communication device (roadside unit) to transmit information (LDM) representative of the acquired position information about the moving objects to the first communication terminal (vehicle).Type: ApplicationFiled: September 21, 2016Publication date: March 30, 2017Inventors: Daisuke OSHIDA, Masakatsu YOKOTA, Yasuhiro SAGESAKA
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Publication number: 20160065367Abstract: Provided is a high-speed and light-weighted authentication system that makes IP address filtering possible and does not impair real-time property even on a network including many and unspecific entities (communication devices). In a communication system that a plurality of communication devices are coupled together such that mutual communication is possible over the network, the communication devices communicate with a server under a secure environment, when authentication has been obtained from the server, random seeds of the same value and individual identifiers are issued to them, each communication device generates the IP address that includes a pseudorandom number and the identifier, and the communication devices establish communication between the communication devices that include the pseudorandom numbers that are mutually the same in their IP addresses.Type: ApplicationFiled: August 26, 2015Publication date: March 3, 2016Inventors: Daisuke OSHIDA, Yoshiyuki SATO, Yasuhiro SAGESAKA, Takeshi ITOME
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Patent number: 8090398Abstract: A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.Type: GrantFiled: April 30, 2008Date of Patent: January 3, 2012Assignee: Renesas Electronics CorporationInventors: Tetsuya Nakagawa, Yuji Hatano, Yasuhiro Sagesaka, Toru Baji, Koki Noguchi
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Publication number: 20080207158Abstract: A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.Type: ApplicationFiled: April 30, 2008Publication date: August 28, 2008Inventors: Tetsuya NAKAGAWA, Yuji Hatano, Yasuhiro Sagesaka, Toru Baji, Koki Noguchi
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Publication number: 20060085563Abstract: A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.Type: ApplicationFiled: November 30, 2005Publication date: April 20, 2006Inventors: Tetsuya Nakagawa, Yuji Hatano, Yasuhiro Sagesaka, Toru Baji, Koki Noguchi
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Patent number: 6993597Abstract: A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.Type: GrantFiled: August 13, 2003Date of Patent: January 31, 2006Assignee: Renesas Technology Corp.Inventors: Tetsuya Nakagawa, Yuji Hatano, Yasuhiro Sagesaka, Toru Baji, Koki Noguchi
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Publication number: 20040049606Abstract: A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.Type: ApplicationFiled: August 13, 2003Publication date: March 11, 2004Inventors: Tetsuya Nakagawa, Yuji Hatano, Yasuhiro Sagesaka, Toru Baji, Koki Noguchi
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Patent number: 6643713Abstract: A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.Type: GrantFiled: December 28, 2001Date of Patent: November 4, 2003Assignee: Hitachi, Ltd.Inventors: Tetsuya Nakagawa, Yuji Hatano, Yasuhiro Sagesaka, Toru Baji, Koki Noguchi
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Publication number: 20020056014Abstract: A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.Type: ApplicationFiled: December 28, 2001Publication date: May 9, 2002Inventors: Tetsuya Nakagawa, Yuji Hatano, Yasuhiro Sagesaka, Toru Baji, Koki Noguchi
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Patent number: 6353863Abstract: A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.Type: GrantFiled: December 1, 1998Date of Patent: March 5, 2002Assignee: Hitachi, Ltd.Inventors: Tetsuya Nakagawa, Yuji Hatano, Yasuhiro Sagesaka, Toru Baji, Koki Noguchi
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Patent number: 5619361Abstract: A base station (5) comprises a base transmitter (6) for transmitting information optically to a plurality of portable stations (1 to 4) at such a predetermined time interval as is designated by portable station designating information. Each of the portable stations (1 to 4) comprises a potable transmitter (7) for transmitting information optically to the base station (5) in response to the transmission, which is designated by the portable station designating information coming from said base station (5), and within the range of the aforementioned time interval immediately after said transmission. Transmissions (ACK1 to ACK4) from the mating portable stations to the base station are individually inserted between the interval periods of the transmissions (REQ1 to REQ4) from the base station (5) to the portable stations (1 to 4) so that the single base station performs optical communications with the plurality of portable stations in a half-duplex time sharing manner.Type: GrantFiled: January 18, 1994Date of Patent: April 8, 1997Assignee: Hitachi, Ltd.Inventors: Yasuhiro Sagesaka, Yoshifumi Kawamura, Junichi Tatezaki, Hideo Wada, Isao Kodama, Atsushi Ogane
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Patent number: 5241679Abstract: A data processor comprises a plurality of registers 1 (registers a to d), a plurality of data saving stack memory devices 2 coupled to the registers 1 for exclusive use thereof, respectively, and an instruction decoder for decoding instructions for controlling the registers 1 and the data saving stack memory devices 2 in accordance with the result of the instruction decoding. In response to an instruction "PUSH", the contents of the registers 1 (registers a to d) are selectively saved to the data saving stack memory device 2. In response to a instruction "POP", the contents of the data saving stack memory devices 2 are selectively restored to the registers 1 (registers a to d). Each of the instructions "PUSH" and "POP" has a field for indicating need or needlessness of the saving and restoration for each of the registers 1 and each of the data saving memories 2.Type: GrantFiled: June 27, 1990Date of Patent: August 31, 1993Assignee: Hitachi Ltd.Inventors: Tetsuya Nakagawa, Masafumi Miyamoto, Yasuhiro Sagesaka, Toru Baji