Abstract: In an input circuit of a semiconductor device, a CMOS inverter has first and second transistors connected in series between an external power supply and ground and complementarily operating in accordance with an input signal. The first and second transistors have a connection point connected to an output terminal. A first switching device is connected in parallel to the second transistor and turned on/off. A comparator compares a voltage from the external power supply with a predetermined reference voltage and outputs a reference signal representing a comparison result. A logic circuit performs a logical operation between the reference signal from the comparator and the input signal supplied to an input terminal of the CMOS inverter and ON/OFF-controls the first switching device on the basis of a logical operation result.

Abstract: In a semiconductor integrated circuit device in which metal assist wires (2) such as aluminum assist wires for operating word lines (1) at high speed are disposed in parallel to the word lines, the metal assist wires (2) are disposed so as to extend to and terminate on halfway positions toward both ends of the word lines (1), and signal/power source lines (10, 11) are formed of the same metal wiring layer as that of the metal assist wires in parallel to digit lines (4) in an area locating from the end portions of the metal assist wires to the end portions of the word lines.

Abstract: A semiconductor storage apparatus includes a memory cell array containing a plurality of memory cells arranged in an array in both directions along a row and a column on a surface of a semiconductor substrate and a plurality of digit line pairs and word lines connected to the memory cell array, sense amplifiers for amplifying potential differences between the lines of the digit line pairs, Y decoders for selecting a predetermined one of the digit line pairs, load circuits for determining the potential of the digit line pairs in response to currents flowing through the digit line pairs, balancer circuits for balancing potential levels of the digit line pairs, and precharge circuits for precharging the potentials of the digit line pairs.

Abstract: Accessed data bits are developed by a sense amplifier unit for driving one of data bus sub-systems associated with a part of a memory cell array, and a data line selecting unit causes output data circuits to be responsive to the accessed data bits on the selected data bus subsystem only, whereby the sense amplifier unit allows the accessed data bits to be propagated at high speed because of reduction of parasitic capacitance.

Abstract: A semiconductor memory device is rescued from a defective product by replacing a column of regular memory cells containing a defective memory cell with a column of redundant memory cells, and allows a multi-bit data code to be read out partially from regular memory cell arrays as well as partially from the column of the redundant memory cells by permanently disabling a regular column address decoder circuit associated with the column of the regular memory cells replaced with the column of the redundant memory cells so that the other memory cell arrays and the column of the redundant memory cells become concurrently accessible.