Patents by Inventor Yasuhiro Shiino
Yasuhiro Shiino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240153560Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.Type: ApplicationFiled: January 17, 2024Publication date: May 9, 2024Applicant: KIOXIA CORPORATIONInventors: Yasuhiro SHIINO, Eietsu TAKAHASHI
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Publication number: 20240087659Abstract: A semiconductor storage device that is capable of improving reliability includes: a non-volatile memory provided with a block including a plurality of memory cell transistors connected to a word line; and a controller configured to monitor a threshold voltage distribution width of the plurality of memory cell transistors after performing at least one of an erasing operation on the block and a preliminary write operation on the plurality of memory cell transistors and to classify the plurality of memory cell transistors according to the threshold voltage distribution width of the plurality of memory cell transistors.Type: ApplicationFiled: February 2, 2023Publication date: March 14, 2024Inventors: Ryota HIRAI, Yasuhiro SHIINO
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Publication number: 20240079065Abstract: According to one embodiment, a semiconductor memory device includes a first memory sub-block and a second memory sub-block arranged in a first direction and a control circuit. The first memory sub-block includes a first memory cell and a first word line connected to the first memory cell. The second memory sub-block includes a second memory cell and a second word line connected to the second memory cell. The control circuit executes a first and a second write operation on the first memory cell. In the first write operation, the control circuit applies a program voltage to the first word line and a first unselect write voltage to the second word line. In the second write operation, the program voltage is applied to the first word line and a second unselect write voltage is applied to the second word line.Type: ApplicationFiled: August 8, 2023Publication date: March 7, 2024Inventors: Yasuhiro SHIINO, Kenrou KIKUCHI
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Patent number: 11915756Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.Type: GrantFiled: May 2, 2022Date of Patent: February 27, 2024Assignee: KIOXIA CORPORATIONInventors: Yasuhiro Shiino, Eietsu Takahashi
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Patent number: 11881267Abstract: A semiconductor memory device includes a substrate, gate electrodes, a semiconductor layer opposed to gate electrodes, an electric charge accumulating layer disposed between gate electrodes and the semiconductor layer, a conductive layer connected to one end portion of the semiconductor layer, and a control circuit electrically connected to gate electrodes and the conductive layer. Gate electrodes include first gate electrodes, second gate electrodes, and third gate electrode. The control circuit is configured to perform an erase operation. The erase operation includes: at least one-time first operation that applies a first voltage to the conductive layer; a second operation performed after the first operation, the second operation applying a second voltage to the third gate electrode; and at least one-time third operation performed after the second operation, the third operation applying a third voltage same as or larger than the first voltage to the conductive layer.Type: GrantFiled: March 9, 2022Date of Patent: January 23, 2024Assignee: KIOXIA CORPORATIONInventors: Manabu Sakaniwa, Yasuhiro Shiino, Kota Nishikawa, Yu Ishiyama, Shinji Suzuki
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Publication number: 20240005999Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.Type: ApplicationFiled: September 15, 2023Publication date: January 4, 2024Applicant: KIOXIA CORPORATIONInventors: Yasuhiro SHIINO, Eietsu TAKAHASHI, Koki UENO
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Patent number: 11817155Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.Type: GrantFiled: February 23, 2023Date of Patent: November 14, 2023Assignee: KIOXIA CORPORATIONInventors: Yasuhiro Shiino, Eietsu Takahashi, Koki Ueno
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Publication number: 20230197167Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.Type: ApplicationFiled: February 23, 2023Publication date: June 22, 2023Applicant: KIOXIA CORPORATIONInventors: Yasuhiro SHIINO, Eietsu TAKAHASHI, Koki UENO
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Patent number: 11621041Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.Type: GrantFiled: March 31, 2021Date of Patent: April 4, 2023Assignee: Kioxia CorporationInventors: Yasuhiro Shiino, Eietsu Takahashi, Koki Ueno
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Publication number: 20230064140Abstract: A second conductor, third conductor, and fourth conductor sandwiches a first layer together with a first semiconductor. The fourth conductor is positioned farther from the first conductor than the third conductor, which is positioned farther from first conductor than the second conductor. A first circuit is configured to apply a first potential to the first and second conductors, apply a second potential lower than the first potential to the third conductor in parallel with the application of the first potential, and apply a third potential higher than the second potential and lower than the first potential to the fourth conductor in parallel with the application of the first potential.Type: ApplicationFiled: March 4, 2022Publication date: March 2, 2023Applicant: Kioxia CorporationInventors: Yasuhiro SHIINO, Masahiko IGA, Shinji SUZUKI
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Publication number: 20230056364Abstract: A semiconductor memory device includes a substrate, gate electrodes, a semiconductor layer opposed to gate electrodes, an electric charge accumulating layer disposed between gate electrodes and the semiconductor layer, a conductive layer connected to one end portion of the semiconductor layer, and a control circuit electrically connected to gate electrodes and the conductive layer. Gate electrodes include first gate electrodes, second gate electrodes, and third gate electrode. The control circuit is configured to perform an erase operation. The erase operation includes: at least one-time first operation that applies a first voltage to the conductive layer; a second operation performed after the first operation, the second operation applying a second voltage to the third gate electrode; and at least one-time third operation performed after the second operation, the third operation applying a third voltage same as or larger than the first voltage to the conductive layer.Type: ApplicationFiled: March 9, 2022Publication date: February 23, 2023Applicant: KIOXIA CORPORATIONInventors: Manabu SAKANIWA, Yasuhiro SHIINO, Kota NISHIKAWA, Yu ISHIYAMA, Shinji SUZUKI
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Patent number: 11557356Abstract: A semiconductor memory device includes a memory block with string units including a plurality of memory strings of memory cell transistors connected in series. Word lines are connected memory cell transistors in a same row and bit lines are respectively connected to one of the memory strings in each string unit. The bit lines are divided into different groups. A control circuit performs erasing on of the memory cell transistors in the memory block. The control circuit executes the erase verification on only a subset of memory strings in each string unit of the memory block rather than all memory strings.Type: GrantFiled: February 26, 2021Date of Patent: January 17, 2023Assignee: KIOXIA CORPORATIONInventors: Yasuhiro Shiino, Masahiko Iga
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Publication number: 20220262444Abstract: A non-volatile memory of an embodiment includes: a memory cell array including a plurality of memory cell transistors; a plurality of word lines connected to a plurality of gates of the plurality of respective memory cell transistors; a VPGM monitor connected to at least one of the plurality of word lines; and a sequencer. When writing voltage is applied to a selected word line selected from among the plurality of word lines at data writing to the memory cell array, the sequencer detects voltage of the selected word line through the VPGM monitor and determines whether detected voltage obtained through the detection has reached a predetermined value.Type: ApplicationFiled: September 1, 2021Publication date: August 18, 2022Applicant: Kioxia CorporationInventors: Ryota HIRAI, Daisuke ARIZONO, Yasuhiro SHIINO, Takuya KUSAKA
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Publication number: 20220262439Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.Type: ApplicationFiled: May 2, 2022Publication date: August 18, 2022Applicant: KIOXIA CORPORATIONInventors: Yasuhiro SHIINO, Eietsu TAKAHASHI
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Patent number: 11355193Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.Type: GrantFiled: October 6, 2020Date of Patent: June 7, 2022Assignee: KIOXIA CORPORATIONInventors: Yasuhiro Shiino, Eietsu Takahashi
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Publication number: 20210280260Abstract: A semiconductor memory device includes a memory block with string units including a plurality of memory strings of memory cell transistors connected in series. Word lines are connected memory cell transistors in a same row and bit lines are respectively connected to one of the memory strings in each string unit. The bit lines are divided into different groups. A control circuit performs erasing on of the memory cell transistors in the memory block. The control circuit executes the erase verification on only a subset of memory strings in each string unit of the memory block rather than all memory strings.Type: ApplicationFiled: February 26, 2021Publication date: September 9, 2021Inventors: Yasuhiro Shiino, Masahiko Iga
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Publication number: 20210217481Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.Type: ApplicationFiled: March 31, 2021Publication date: July 15, 2021Applicant: Toshiba Memory CorporationInventors: Yasuhiro SHIINO, Eietsu TAKAHASHI, Koki UENO
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Patent number: 11004520Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.Type: GrantFiled: September 21, 2020Date of Patent: May 11, 2021Assignee: Toshiba Memory CorporationInventors: Yasuhiro Shiino, Eietsu Takahashi, Koki Ueno
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Publication number: 20210020249Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.Type: ApplicationFiled: October 6, 2020Publication date: January 21, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventors: Yasuhiro SHIINO, Eietsu TAKAHASHI
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Publication number: 20210005270Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.Type: ApplicationFiled: September 21, 2020Publication date: January 7, 2021Applicant: Toshiba Memory CorporationInventors: Yasuhiro SHIINO, Eietsu TAKAHASHI, Koki UENO