Patents by Inventor Yasuhiro Shimamoto
Yasuhiro Shimamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11260370Abstract: A composition for exhaust gas purification including first alumina including alumina containing lanthanum and second alumina including alumina containing lanthanum. The first alumina has a higher lanthanum content than the second alumina. The second alumina has a larger particle size than the first alumina. The lanthanum content of the first alumina is preferably 2 to 12 mass %, in terms of oxide, based on the total mass of alumina and lanthanum oxide of the first alumina. The lanthanum content of the second alumina is preferably 9 mass % or less, in terms of oxide, based on the total mass of alumina and lanthanum oxide of the second alumina.Type: GrantFiled: March 26, 2019Date of Patent: March 1, 2022Assignee: Mitsui Mining & Smelting Co., Ltd.Inventors: Yasuhiro Shimamoto, Hironori Iwakura, Tomoya Hoshinoo
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Publication number: 20200376466Abstract: A composition for exhaust gas purification including first alumina including alumina containing lanthanum and second alumina including alumina containing lanthanum. The first alumina has a higher lanthanum content than the second alumina. The second alumina has a larger particle size than the first alumina. The lanthanum content of the first alumina is preferably 2 to 12 mass %, in terms of oxide, based on the total mass of alumina and lanthanum oxide of the first alumina. The lanthanum content of the second alumina is preferably 9 mass % or less, in terms of oxide, based on the total mass of alumina and lanthanum oxide of the second alumina.Type: ApplicationFiled: March 26, 2019Publication date: December 3, 2020Inventors: Yasuhiro SHIMAMOTO, Hironori IWAKURA, Tomoya HOSHINOO
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Patent number: 9673339Abstract: In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p?-type polysilicon film with a high impurity concentration deposited thereon.Type: GrantFiled: August 28, 2015Date of Patent: June 6, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Itaru Yanagi, Toshiyuki Mine, Hirotaka Hamamura, Digh Hisamoto, Yasuhiro Shimamoto
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Patent number: 9318558Abstract: The present invention is to cause high channel mobility and a high threshold voltage to coexist in a SiC-MOSFET power device which uses a SiC substrate. The SiC MOSFET which is provided with a layered insulation film having electric charge trap characteristics on a gate insulation film has an irregular threshold voltage in a channel length direction of the SiC MOSFET, and in particular, has a shorter area having a maximum threshold voltage in the channel length direction compared to an area having other threshold voltages.Type: GrantFiled: July 9, 2012Date of Patent: April 19, 2016Assignee: Hitachi, Ltd.Inventors: Toshiyuki Mine, Yasuhiro Shimamoto, Hirotaka Hamamura
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Patent number: 9312385Abstract: A technique for improving characteristics of a semiconductor device (DMOSFET) is provided. A semiconductor device is configured so as to include: an n-type source layer (102) disposed on an upper portion of a first surface side of an SiC substrate (106); a p body layer (103) which surrounds the source layer and has a channel region; an n?-type drift layer (107) which is in contact with the p body layer (103); a gate electrode (116) which is disposed on an upper portion of the channel region via a gate insulating film; and a first p+ layer (109) which is disposed in the p body layer (103), extends to a portion below the n+ source layer (102), and serves as a buried semiconductor region having an impurity concentration higher than that of the p body layer (103). In this manner, since the first p+ layer (109) is formed in the middle of the p body layer (103), it is possible to reduce the diffusion resistance of the p body layer (103). Thus, it is possible to make a parasitic bipolar transistor harder to turn on.Type: GrantFiled: June 7, 2012Date of Patent: April 12, 2016Assignee: Hitachi, Ltd.Inventors: Daisuke Matsumoto, Naoki Tega, Yasuhiro Shimamoto
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Publication number: 20150372151Abstract: In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p?-type polysilicon film with a high impurity concentration deposited thereon.Type: ApplicationFiled: August 28, 2015Publication date: December 24, 2015Inventors: Itaru YANAGI, Toshiyuki MINE, Hirotaka HAMAMURA, Digh HISAMOTO, Yasuhiro SHIMAMOTO
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Patent number: 9214516Abstract: In a SiC-MOSFET power device for which a SiC substrate is used, a laminated insulating film having a charge-trapping characteristic is employed as a gate insulating film of the SiC-DiMOSFET, and charges are injected into the laminated insulating film, thereby suppressing a change in the gate threshold voltage.Type: GrantFiled: March 30, 2012Date of Patent: December 15, 2015Assignee: Hitachi, Ltd.Inventors: Toshiyuki Mine, Yasuhiro Shimamoto, Hirotaka Hamamura
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Patent number: 9117849Abstract: A method and apparatus of forming a nonvolatile semiconductor device including forming a first gate insulating film on a main surface of a first semiconductor region, forming a first gate electrode on the first gate insulating film, forming a second gate insulating film, forming a second gate electrode over a first side surface of the first gate electrode, selectively removing the second gate insulating film, etching the second gate insulating film kept between the second gate electrode and a main surface of the first semiconductor region in order to form an etched charge storage layer, introducing first impurities in the first semiconductor region in a self-aligned manner to the second gate electrode in order to form a second semiconductor region, annealing the semiconductor substrate to extend the second semiconductor region to an area under the second gate electrode.Type: GrantFiled: July 8, 2014Date of Patent: August 25, 2015Assignee: Renesas Electronics CorporationInventors: Kenichi Akita, Daisuke Okada, Keisuke Kuwahara, Yasufumi Morimoto, Yasuhiro Shimamoto, Kan Yasui, Tsuyoshi Arigane, Tetsuya Ishimaru
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Patent number: 9117836Abstract: A SiC MOSFET has a subject that resistance in the source region is increased when annealing for metal silicidation is performed to a source region before forming the gate insulating film, the metal silicide layer of the source region is oxidized by an oxidizing treatment (including oxynitriding treatment) when the gate insulating film is formed. When a metal silicide layer to be formed on the surface of a SiC epitaxial substrate is formed before forming a gate insulating film interface layer (oxide film), and an anti-oxidation film for the metal silicide is formed on the metal silicide layer, it is possible to suppress oxidation of the metal silicide layer by the oxidizing treatment upon forming the gate insulating film interface layer and the resistance of the source region can be decreased without lowering the channel mobility.Type: GrantFiled: January 12, 2012Date of Patent: August 25, 2015Assignee: Hitachi, Ltd.Inventors: Naoki Tega, Yasuhiro Shimamoto, Yuki Mori, Hirotaka Hamamura, Hiroyuki Okino, Digh Hisamoto
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Publication number: 20150179744Abstract: The present invention is to cause high channel mobility and a high threshold voltage to coexist in a SiC-MOSFET power device which uses a SiC substrate. The SiC MOSFET which is provided with a layered insulation film having electric charge trap characteristics on a gate insulation film has an irregular threshold voltage in a channel length direction of the SiC MOSFET, and in particular, has a shorter area having a maximum threshold voltage in the channel length direction compared to an area having other threshold voltages.Type: ApplicationFiled: July 9, 2012Publication date: June 25, 2015Applicant: HITACHI , LTD.Inventors: Toshiyuki Mine, Yasuhiro Shimamoto, Hirotaka Hamamura
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Patent number: 9029979Abstract: A trench groove is formed and a silicon oxide film is buried in the periphery of a channel region of (0001) surface 4h-SiC semiconductor element. The oxide film in the trench groove is defined in such a planar layout that a tensile strain is applied along the direction of the c-axis and a compressive strain is applied along two or more of axes on a plane perpendicular to the c-axis. For example, trench grooves buried with an oxide film may be configured to such a layout that they are in a trigonal shape surrounding the channel, or are arranged symmetrically with respect to the channel as a center when arranged discretely.Type: GrantFiled: November 23, 2012Date of Patent: May 12, 2015Assignee: Hitachi, Ltd.Inventors: Hiroyuki Yoshimoto, Ryuta Tsuchiya, Naoki Tega, Digh Hisamoto, Yasuhiro Shimamoto, Yuki Mori
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Patent number: 9000448Abstract: A MOSFET having a high mobility may be obtained by introducing nitrogen to the channel region or the interface between the gate dielectric film and the SiC substrate of the SiC MOSFET, but there is a problem that a normally-on MOSFET is obtained. For realizing both a high mobility and normally-off, and for providing a SiC MOSFET having further high reliability, nitrogen is introduced to the channel region of the SiC substrate or the interface between the gate dielectric film and the SiC substrate, and furthermore a metal oxide film having a thickness of 10%, or less of the total thickness of the gate dielectric film is inserted in the gate dielectric film.Type: GrantFiled: March 29, 2011Date of Patent: April 7, 2015Assignee: Hitachi, Ltd.Inventors: Hirotaka Hamamura, Yasuhiro Shimamoto, Hiroyuki Okino
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Publication number: 20140327066Abstract: In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p|-type polysilicon film with a high impurity concentration deposited thereon.Type: ApplicationFiled: July 18, 2014Publication date: November 6, 2014Inventors: Itaru YANAGI, Toshiyuki MINE, Hirotaka HAMAMURA, Digh HISAMOTO, Yasuhiro SHIMAMOTO
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Publication number: 20140322874Abstract: A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.Type: ApplicationFiled: July 8, 2014Publication date: October 30, 2014Inventors: Kenichi Akita, Daisuke Okada, Keisuke Kuwahara, Yasufumi Morimoto, Yasuhiro Shimamoto, Kan Yasui, Tsuyoshi Arigane, Tetsuya Ishimaru
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Patent number: 8823110Abstract: Disclosed is a semiconductor device including a first MISFET of an n channel type and a second MISFET of a p channel type, each of the MISFETs being configured with a gate insulating film featuring a silicon oxide film or a silicon oxynitride film and a gate electrode including a conductive silicon film positioned on the gate insulating film. Metal elements such as Hf are introduced near the interface between the gate electrode and the gate insulating film in both the first and second MISFETs such that metal atoms with a surface density of 1×1013 to 5×1014 atoms/cm2 are contained near the interface and each of the first and second MISFETs having a channel region containing an impurity the concentration of which is equal to or lower than 1.2×1018/cm3.Type: GrantFiled: July 18, 2013Date of Patent: September 2, 2014Assignee: Renesas Electronics CorporationInventors: Yasuhiro Shimamoto, Jiro Yugami, Masao Inoue, Masaharu Mizutani
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Publication number: 20140239392Abstract: A technique for improving characteristics of a semiconductor device (DMOSFET) is provided. A semiconductor device is configured so as to include: an n-type source layer (102) disposed on an upper portion of a first surface side of an SiC substrate (106); a p body layer (103) which surrounds the source layer and has a channel region; an n?-type drift layer (107) which is in contact with the p body layer (103); a gate electrode (116) which is disposed on an upper portion of the channel region via a gate insulating film; and a first p+ layer (109) which is disposed in the p body layer (103), extends to a portion below the n+ source layer (102), and serves as a buried semiconductor region having an impurity concentration higher than that of the p body layer (103). In this manner, since the first p+ layer (109) is formed in the middle of the p body layer (103), it is possible to reduce the diffusion resistance of the p body layer (103). Thus, it is possible to make a parasitic bipolar transistor harder to turn on.Type: ApplicationFiled: June 7, 2012Publication date: August 28, 2014Inventors: Daisuke Matsumoto, Naoki Tega, Yasuhiro Shimamoto
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Patent number: 8816426Abstract: In a non-volatile memory, writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film, which serves as a charge accumulation layer. The gate electrode of a memory cell has a laminated structure made of a plurality of polysilicon films with different impurity concentrations. In a two-layered structure the gate electrode has a p-type polysilicon film with a low impurity concentration and a p+-type polysilicon film with a high impurity concentration deposited thereon. Holes are injected into the charge accumulation layer from the gate electrode.Type: GrantFiled: March 17, 2013Date of Patent: August 26, 2014Assignee: Renesas Electronics CorporationInventors: Itaru Yanagi, Toshiyuki Mine, Hirotaka Hamamura, Digh Hisamoto, Yasuhiro Shimamoto
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Publication number: 20140217422Abstract: In a SiC-MOSFET power device for which a SiC substrate is used, a laminated insulating film having a charge-trapping characteristic is employed as a gate insulating film of the SiC-DiMOSFET, and charges are injected into the laminated insulating film, thereby suppressing a change in the gate threshold voltage.Type: ApplicationFiled: March 30, 2012Publication date: August 7, 2014Inventors: Toshiyuki Mine, Yasuhiro Shimamoto, Hirotaka Hamamura
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Patent number: 8796756Abstract: A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.Type: GrantFiled: January 31, 2013Date of Patent: August 5, 2014Assignee: Renesas Electronics CorporationInventors: Kenichi Akita, Daisuke Okada, Keisuke Kuwahara, Yasafumi Morimoto, Yasuhiro Shimamoto, Kan Yasui, Tsuyoshi Arigane, Tetsuya Ishimaru
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Publication number: 20140092688Abstract: In a split gate MONOS memory which carries out rewrite by hot carrier injection, retention characteristics are improved. A select gate electrode of a memory cell is connected to a select gate line, and a memory gate electrode is connected to a memory gate line. A drain region is connected to a bit line, and a source region is connected to a source line. Furthermore, a well line is connected to a p type well region in which the memory cell is formed. When write to the memory cell is to be carried out, write by a source side injection method is carried out while applying a negative voltage to the p type well region via the well line.Type: ApplicationFiled: December 9, 2013Publication date: April 3, 2014Applicant: Renesas Electronics CorporationInventors: Tetsuya Ishimaru, Yasuhiro Shimamoto, Hideo Kasai, Yutaka Okuyama, Tsuyoshi Arigane