Abstract: A PFC signal generation circuit which generates a PFC signal to control a PFC circuit including a first inductor L1 connected to a first switch NM1 and a second inductor L2 connected to a second switch NM2 includes: a counter 101 whose count value is cleared based on a first timing when a zero current of the first inductor L1 is detected; a counter clear control circuit 202 that clears the count value after waiting until a cycle lower limit is reached, when the first timing is below the cycle lower limit; a first control signal output unit 109 that outputs a first PFC signal to turn on the first switch NM1 at a timing when the count value is cleared; and a second control signal output unit 117 that outputs a second PFC signal to turn on the second switch NM2 based on a second timing when a zero current of the second inductor L2 is detected. This leads to an improvement in power factor correction by the PFC circuit.

Abstract: A PFC signal generation circuit which generates a PFC signal to control a PFC circuit including a first inductor connected to a first switch and a second inductor connected to a second switch includes: a first control signal output circuit that outputs a first PFC signal to turn on the first switch at a zero current detection timing of the first inductor; a timing adjustment circuit that generates a control signal to turn on the second switch after waiting until a target timing, when a zero current detection timing of the second inductor is earlier than the target timing, and to turn on the second switch at a target timing in a subsequent cycle, when it is later than an allowable period from the target timing; and a second control signal output circuit that generates a second PFC signal to turn on the second switch according to a control signal.

Abstract: A PFC signal generation circuit which generates a PFC signal to control a PFC circuit including a first inductor L1 connected to a first switch NM1 and a second inductor L2 connected to a second switch NM2 includes: a counter 101 whose count value is cleared based on a first timing when a zero current of the first inductor L1 is detected; a counter clear control circuit 202 that clears the count value after waiting until a cycle lower limit is reached, when the first timing is below the cycle lower limit; a first control signal output unit 109 that outputs a first PFC signal to turn on the first switch NM1 at a timing when the count value is cleared; and a second control signal output unit 117 that outputs a second PFC signal to turn on the second switch NM2 based on a second timing when a zero current of the second inductor L2 is detected. This leads to an improvement in power factor correction by the PFC circuit.

Abstract: A PFC signal generation circuit which generates a PFC signal to control a PFC circuit including a first inductor connected to a first switch and a second inductor connected to a second switch includes: a counter whose count value is cleared based on a first timing when a zero current of the first inductor is detected; a counter clear control circuit that clears the counter value after waiting until a cycle lower limit is reached, when the first timing is below the cycle lower limit; a first control signal output unit that outputs a first PFC signal to turn on the first switch at a timing when the count value is cleared; and a second control signal output unit that outputs a second PFC signal to turn on the second switch based on a second timing when a zero current of the second inductor is detected.

Abstract: A PFC signal generation circuit which generates a PFC signal to control a PFC circuit including a first inductor connected to a first switch and a second inductor connected to a second switch includes: a first control signal output circuit that outputs a first PFC signal to turn on the first switch at a zero current detection timing of the first inductor; a timing adjustment circuit that generates a control signal to turn on the second switch after waiting until a target timing, when a zero current detection timing of the second inductor is earlier than the target timing, and to turn on the second switch at a target timing in a subsequent cycle, when it is later than an allowable period from the target timing; and a second control signal output circuit that generates a second PFC signal to turn on the second switch according to a control signal.

Abstract: A PFC signal generation circuit which generates a PFC signal to control a PFC circuit including a first inductor connected to a first switch and a second inductor connected to a second switch includes: a first control signal output circuit that outputs a first PFC signal to turn on the first switch at a zero current detection timing of the first inductor; a timing adjustment circuit that generates a control signal to turn on the second switch after waiting until a target timing, when a zero current detection timing of the second inductor is earlier than the target timing, and to turn on the second switch at a target timing in a subsequent cycle, when it is later than an allowable period from the target timing; and a second control signal output circuit that generates a second PFC signal to turn on the second switch according to a control signal.

Abstract: A timer unit having a first output mode and a second output mode, the timer unit includes a first register that stores a first value, a second register that stores a second value, a third register that stores a third value, a counter that generates a count signal based on the first value, and an output circuit that outputs a first output signal and a second output signal. When the timer unit is set in the first output mode, the output circuit outputs the first output signal having a pulse width determined by the count signal and the second value, and outputs the second output signal having a pulse width determined by the count signal and the third value. When the timer unit is set in the second output mode, the output circuit outputs the first output signal having a pulse width determined by the count signal, the second value and the third value.

Abstract: A timer unit having a first output mode and a second output mode, the timer unit includes a first register that stores a first value, a second register that stores a second value, a third register that stores a third value, a counter that generates a count signal based on the first value, and an output circuit that outputs a first output signal and a second output signal. When the timer unit is set in the first output mode, the output circuit outputs the first output signal having a pulse width determined by the count signal and the second value, and outputs the second output signal having a pulse width determined by the count signal and the third value. When the timer unit is set in the second output mode, the output circuit outputs the first output signal having a pulse width determined by the count signal, the second value and the third value.

Abstract: A timer unit includes a first selector that receives a fixed value and a first enable signal, a second selector that receives the fixed value and a count cycle signal, a third selector that receives an output of the second selector, the count cycle signal, and a second enable signal, a first counter circuit that starts counting in response to an output of the first selector, and that generates the count cycle signal and a first counter circuit output signal indicating that a count value approaches a predetermined value, a second counter circuit that starts counting in response to an output of the third selector, and that generates a second counter circuit output signal, a first output signal generator that receives the first counter circuit output signal and the second counter circuit output signal to generate a first output signal, and a second output signal generator.

Abstract: A PFC signal generation circuit which generates a PFC signal to control a PFC circuit including a first inductor connected to a first switch and a second inductor connected to a second switch includes: a counter whose count value is cleared based on a first timing when a zero current of the first inductor is detected; a counter clear control circuit that clears the counter value after waiting until a cycle lower limit is reached, when the first timing is below the cycle lower limit; a first control signal output unit that outputs a first PFC signal to turn on the first switch at a timing when the count value is cleared; and a second control signal output unit that outputs a second PFC signal to turn on the second switch based on a second timing when a zero current of the second inductor is detected.

Abstract: A PFC signal generation circuit which generates a PFC signal to control a PFC circuit including a first inductor connected to a first switch and a second inductor connected to a second switch includes: a first control signal output circuit that outputs a first PFC signal to turn on the first switch at a zero current detection timing of the first inductor; a timing adjustment circuit that generates a control signal to turn on the second switch after waiting until a target timing, when a zero current detection timing of the second inductor is earlier than the target timing, and to turn on the second switch at a target timing in a subsequent cycle, when it is later than an allowable period from the target timing; and a second control signal output circuit that generates a second PFC signal to turn on the second switch according to a control signal.

Abstract: A timer unit includes a first selector that receives a fixed value and a first enable signal, a second selector that receives the fixed value and a count cycle signal, a third selector that receives an output of the second selector, the count cycle signal, and a second enable signal, a first counter circuit that starts counting in response to an output of the first selector, and that generates the count cycle signal and a first counter circuit output signal indicating that a count value approaches a predetermined value, a second counter circuit that starts counting in response to an output of the third selector, and that generates a second counter circuit output signal, a first output signal generator that receives the first counter circuit output signal and the second counter circuit output signal to generate a first output signal, and a second output signal generator.

Abstract: First and second counter circuits output a signal based on a trigger signal and a clock signal respectively. A selection circuit selects first to fourth signals as the trigger signal, the clock signal, the trigger signal and the clock signal. In a first output mode, an output circuit outputs signals exhibiting normal-phase and reversed-phase PWM waveforms based on both of the signals of the first and second counter circuits. In a second output mode, the output circuit outputs signals that are each based only on either of the signals of the first and second counter circuits.

Abstract: A cylindrical body arranged between a shaft body and a blade of a horizontal axis wind turbine is constituted of a cylindrical barrel portion, a first flange portion fixed to a first end of the barrel portion so that the blade is connected thereto, and a second flange portion fixed to a second end of the barrel portion and connected to the shaft body. The barrel portion is constituted of a cylindrically formed rubber stock and a plurality of filamentary bodies embedded in the rubber stock and arranged in a state inclined by a prescribed angle with respect to a direction parallel to an axial direction. When tensile force F develops in the barrel portion due to centrifugal force resulting from rotation of the blade, both opening ends of the barrel portion twistedly rotate due to actions of the filamentary bodies. Thus, it follows that the pitch angle of the blade connected to the first flange portion automatically varies with a wind speed.

Abstract: First and second counter circuits output a signal based on a trigger signal and a clock signal respectively. A selection circuit selects first to fourth signals as the trigger signal, the clock signal, the trigger signal and the clock signal. In a first output mode, an output circuit outputs signals exhibiting normal-phase and reversed-phase PWM waveforms based on both of the signals of the first and second counter circuits. In a second output mode, the output circuit outputs signals that are each based only on either of the signals of the first and second counter circuits.

Abstract: In the synchronous compensator, a load generator loads a bit counter with data in dependence upon whether or not a detection signal from a UW detector falls within the range indicated by an enable signal from a synchronous compensator circuit, thereby excluding the detection signal appearing far from the normal position to establish an appropriate synchronous compensation. The synchronous compensation is thus accomplished on the basis of normally received signal waves without picking up abnormal waves supposed as reflected waves.

Abstract: In the synchronous compensator, a load generator loads a bit counter with data in dependence upon whether or not a detection signal from a UW detector falls within the range indicated by an enable signal from a synchronous compensator circuit, thereby excluding the detection signal appearing far from the normal position to establish an appropriate synchronous compensation. The synchronous compensation is thus accomplished on the basis of normally received signal waves without picking up abnormal waves supposed as reflected waves.