Patents by Inventor Yasuhiro Tamada

Yasuhiro Tamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8304856
    Abstract: A serially-connected diode pair made of diodes having a high withstand voltage and a low on-resistance is formed based on a high withstand voltage vertical PNP bipolar transistor process technology. Two of the diode pairs are connected in parallel to form a bridge so that there is formed a high-efficiency full-wave rectifier circuit that is free from a leakage current due to a parasitic transistor. The serially-connected diode pair is formed by connecting a diode composed of a P type semiconductor substrate, that makes an anode, and an N type buried layer, that makes a cathode, and a diode composed of a P+ type conductive layer, that makes an anode, and an N type epitaxial layer, that makes a cathode, in series with an electrode AC1.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: November 6, 2012
    Assignees: Sanyo Semiconductor Co., Ltd., Sanyo Semiconductor Manufacturing Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Keiji Mita, Yasuhiro Tamada, Masao Takahashi, Takao Maruyama
  • Patent number: 8080863
    Abstract: A conventional semiconductor device, for example, a lateral PNP transistor has a problem that it is difficult to obtain a desired current-amplification factor while maintaining a breakdown voltage characteristic without increasing the device size. In a semiconductor device, that is a lateral PNP transistor, according to the present invention, an N type epitaxial layer is formed on a P type single crystal silicon substrate. The epitaxial layer is used as a base region. Moreover, molybdenum (Mo) is diffused in the substrate and the epitaxial layer. With this structure, the base current is adjusted, and thereby a desired current-amplification factor (hFE) of the lateral PNP transistor is achieved.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: December 20, 2011
    Inventors: Keiji Mita, Yasuhiro Tamada, Kentaro Ooka
  • Publication number: 20110079880
    Abstract: A serially-connected diode pair made of diodes having a high withstand voltage and a low on-resistance is formed based on a high withstand voltage vertical PNP bipolar transistor process technology. Two of the diode pairs are connected in parallel to form a bridge so that there is formed a high-efficiency full-wave rectifier circuit that is free from a leakage current due to a parasitic transistor. The serially-connected diode pair is formed by connecting a diode composed of a P type semiconductor substrate, that makes an anode, and an N type buried layer, that makes a cathode, and a diode composed of a P+ type conductive layer, that makes an anode, and an N type epitaxial layer, that makes a cathode, in series with an electrode AC1.
    Type: Application
    Filed: September 13, 2010
    Publication date: April 7, 2011
    Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd.
    Inventors: Keiji Mita, Yasuhiro Tamada, Masao Takahashi, Takao Maruyama
  • Publication number: 20080023796
    Abstract: A conventional semiconductor device, for example, a lateral PNP transistor has a problem that it is difficult to obtain a desired current-amplification factor while maintaining a breakdown voltage characteristic without increasing the device size. In a semiconductor device, that is a lateral PNP transistor, according to the present invention, an N type epitaxial layer is formed on a P type single crystal silicon substrate. The epitaxial layer is used as a base region. Moreover, molybdenum (Mo) is diffused in the substrate and the epitaxial layer. With this structure, the base current is adjusted, and thereby a desired current-amplification factor (hFE) of the lateral PNP transistor is achieved.
    Type: Application
    Filed: July 27, 2007
    Publication date: January 31, 2008
    Applicants: SANYO ELECTRIC CO., LTD., SANYO SEMICONDUCTOR CO., LTD., SANYO SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Keiji Mita, Yasuhiro Tamada, Kentaro Ooka
  • Patent number: 5141881
    Abstract: A method of making a semiconductor integrated circuit provided with an isolating region constituted of an upper and lower isolating regions, and integrated circuit element regions is disclosed, wherein: the lower isolating region is diffused upward to a depth of a little more than half the thickness of an epitaxial layer to link with the upper isolating region prior to a doping of the upper isolating region; the doping of the lower isolating region and integrated circuit element regions, is implemented by means of ion implantation through a resist film which is capable of blocking ions implanted and in which specified doping windows have been formed in advance, and a SiO.sub.2 film is used as a reference mask in an ion implanting step, and the respective borders of the upper isolating region and the specified regions of the circuit elements is determined by self-alignment.
    Type: Grant
    Filed: April 18, 1990
    Date of Patent: August 25, 1992
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kazuo Takeda, Toshimasa Sadakata, Teruo Tabata, Nobuyuki Sekikawa, Tadayoshi Takada, Yasuhiro Tamada, Yoshiaki Sano