Abstract: A non-volatile memory includes a plurality of word lines, power supply units are provided for word line columns, a different unit voltage is applied for each of power supply units depending on whether a selected memory cell exists in the column, a switching mechanism in each power supply unit is switched by the word line depending on a voltage value on a control line, a charge storage gate voltage or inhibition gate voltage is applied for each of the word lines so that the inhibition gate voltage value and a bit line voltage value can be freely set for each of the word line columns to values at which occurrence of disturbance can be suppressed. A plurality of power supply units are connected to the control line in a common row direction, and a row-direction address decoder, which is independent for each of the word line columns is not required.

Abstract: In a non-volatile semiconductor memory device capable of programming SRAM data in an SRAM into a non-volatile memory unit while implementing a high-speed operation in the SRAM, a voltage required to program the SRAM data into the non-volatile memory unit can be lowered. Thus, the SRAM can be operated at high speed with a low power supply voltage because the thickness of a gate insulating film of each of a first access transistor, a second access transistor, a first load transistor, a second load transistor, a first drive transistor, and a second drive transistor constituting the SRAM connected to the non-volatile memory unit can be set to 4 [nm] or less. Therefore, the SRAM data in the SRAM can be programmed into the non-volatile memory unit while a high-speed operation in the SRAM can be implemented.

Abstract: To propose a non-volatile semiconductor memory device capable of suppressing occurrence of disturbance more greatly than in a conventional technique while achieving miniaturization. A plurality of word lines are formed in a matrix in the non-volatile semiconductor memory device, power supply units are respectively provided for word line columns (memory wells), a different unit voltage is applied for each of power supply units depending on whether or not a selected memory cell exists in the word line column, a switching mechanism in each of the power supply units is switched by the word line depending on a value of a voltage on a control line, a charge storage gate voltage or a charge storage inhibition gate voltage is individually applied for each of the word lines so that the charge storage inhibition gate voltage value and a bit line voltage value can be freely set for each of the word line columns to values at which occurrence of disturbance can be suppressed.

Abstract: To propose a non-volatile semiconductor memory device capable of injecting charge into a floating gate by source side injection even in a single-layer gate structure. In a non-volatile semiconductor memory device (1), while each of the memory transistor (MGA1) and the switch transistor (SGA) is made to have a single-layer gate structure, when a selected memory cell (3a) is turned on by applying a high voltage to one end of a memory transistor (MGA1) from a source line (SL) during data programming and applying a low voltage to one end of the switch transistor (SGA) from a bit line (BL1), a voltage drop occurs in a low-concentration impurity extension region (ET2) in the memory transistor (MGA1) between the source line (SL) and the bit line (BL1) to generate an intense electric field, and charge can be injected into the floating gate (FG) by source side injection using the intense electric field.

Abstract: Provided is a non-volatile semiconductor memory device capable of reliably preventing a malfunction of a read transistor without increasing the number of bit lines. In a non-volatile semi conductor memory device (1), program transistors (5a, 5b) and erase transistors (3a, 3b) serving as charge transfer paths during data programming and erasure are provided while a second bit line (BLN1) connected to the program transistor (5a) in a first cell (2a) for performing data programming also serves as a reading bit line in the other second cell (2b) by switching switch transistors (SWa, SWb) so that malfunctions of read transistors (4a, 4b) that occur because the read transistors are used for data programming and erasure can be reliably prevented without the number of bit lines being increased.

Abstract: A non-volatile semiconductor memory device is proposed whereby voltage can be more flexibly set in accumulating electric charges into a selected memory cell transistor in comparison with a conventional device. In a non-volatile semiconductor memory device (1), when a selected memory cell transistor (115) is caused to accumulate electric charges, high voltage as writing prevention voltage is applied from a PMOS transistor (9b) while low voltage as writing voltage is applied from an NMOS transistor (15a). Thus, a role of applying voltage to either the selected memory cell transistor (115) or a non-selected memory cell transistor (116) is shared by the PMOS transistor (9b) and the NMOS transistor (15a). Therefore, the gate voltage and the source voltage of the PMOS transistor (9b) and those of the NMOS transistor (15a) can be separately adjusted, and gate-to-substrate voltage thereof can be finally set to be, for instance, 4[V] or etc.

Abstract: A non-volatile semiconductor memory device is proposed that has an unprecedented novel structure in which carriers can be injected into a floating gate by applying various voltages of the same polarity.

Abstract: In a non-volatile semiconductor memory device, it is only necessary that, at the time of data writing, a voltage drop is caused in a high resistance region. Therefore, the value of voltage applied to a gate electrode can be reduced as compared with a conventional device. In correspondence with the reduction in the value of applied voltage, it is possible to reduce the film thickness of a gate insulating film of memory transistors, and further the film thickness of the gate insulating film of a peripheral transistor for controlling the memory transistors. As a result, the circuit configuration of the non-volatile semiconductor memory device can be reduced in size as compared with the conventional device.

Abstract: A non-volatile semiconductor memory device is proposed whereby voltage can be more flexibly set in accumulating electric charges into a selected memory cell transistor in comparison with a conventional device. In a non-volatile semiconductor memory device (1), when a selected memory cell transistor (115) is caused to accumulate electric charges, high voltage as writing prevention voltage is applied from a PMOS transistor (9b) while low voltage as writing voltage is applied from an NMOS transistor (15a). Thus, a role of applying voltage to either the selected memory cell transistor (115) or a non-selected memory cell transistor (116) is shared by the PMOS transistor (9b) and the NMOS transistor (15a). Therefore, the gate voltage and the source voltage of the PMOS transistor (9b) and those of the NMOS transistor (15a) can be separately adjusted, and gate-to-substrate voltage thereof can be finally set to be, for instance, 4[V] or etc.

Abstract: The performance of a semiconductor device including a nonvolatile memory is enhanced. Each of nonvolatile memory cells arranged over a silicon substrate includes: a first n-well; a second n-well formed in a place different from the place thereof; a selection transistor formed in the first n-well; and an electric charge storage portion having a floating gate electrode and a storage portion p-well. The floating gate electrode is so placed that it overlaps with part of the first n-well and the second n-well. The storage portion p-well is placed in the first n-well so that it partly overlaps with the floating gate electrode. In this nonvolatile memory cell, memory information is erased by applying positive voltage to the second n-well to discharge electrons in the floating gate electrode to the second n-well.

Abstract: The performance of a semiconductor device including a nonvolatile memory is enhanced. Each of nonvolatile memory cells arranged over a silicon substrate includes: a first n-well; a second n-well formed in a place different from the place thereof; a selection transistor formed in the first n-well; and an electric charge storage portion having a floating gate electrode and a storage portion p-well. The floating gate electrode is so placed that it overlaps with part of the first n-well and the second n-well. The storage portion p-well is placed in the first n-well so that it partly overlaps with the floating gate electrode. In this nonvolatile memory cell, memory information is erased by applying positive voltage to the second n-well to discharge electrons in the floating gate electrode to the second n-well.

Abstract: Processing of memory cells forming a nonvolatile memory in a semiconductor device. A second polysilicon film is formed in such a manner as to cover a first polysilicon film and a dummy gate electrode. Thus, the second polysilicon film is formed reflecting the shapes of a step difference portion and a gap groove. Particularly, in the second polysilicon film covering the gap groove, a concave part is formed. Subsequently, over the second polysilicon film, an antireflection film is formed. Thus, the antireflection film having high flowability flows from the higher region to the lower region of the step difference portion, but is stored in a sufficient amount in the concave part. Accordingly, the antireflection film is supplied from the concave part so as to compensate for the amount of the antireflection film to flow out therefrom.

Abstract: There is provided a technology capable of improving the processing precision of memory cells forming a nonvolatile memory in a semiconductor device including the nonvolatile memory. A second polysilicon film is formed in such a manner as to cover a first polysilicon film and a dummy gate electrode. Thus, the second polysilicon film is formed reflecting the shapes of a step difference portion and a gap groove. Particularly, in the second polysilicon film covering the gap groove, a concave part is formed. Subsequently, over the second polysilicon film, an antireflection film is formed. Thus, the antireflection film having high flowability flows from the higher region to the lower region of the step difference portion, but is stored in a sufficient amount in the concave part. Accordingly, the antireflection film is supplied from the concave part so as to compensate for the amount of the antireflection film to flow out therefrom.

Abstract: In processing memory cells for forming a nonvolatile memory in a semiconductor device, a second polysilicon film is formed in such a manner as to cover a first polysilicon film and a dummy gate electrode. Thus, the second polysilicon film is formed reflecting the shapes of a step difference portion and a gap groove. Particularly, in the second polysilicon film covering the gap groove, a concave part is formed. Subsequently, over the second polysilicon film, an antireflection film is formed. Thus, the antireflection film having high flowability flows from the higher region to the lower region of the step difference portion, but is stored in a sufficient amount in the concave part. Accordingly, the antireflection film is supplied from the concave part so as to compensate for the amount of the antireflection film to flow out therefrom.

Abstract: Provided is a manufacturing method of a semiconductor device, which comprises forming a film stack of a gate insulating film, a charge storage film, insulating film, polysilicon film, silicon oxide film, silicon nitride film and cap insulating film over a semiconductor substrate; removing the film stack by photolithography and etching from a low breakdown voltage MISFET formation region and a high breakdown voltage MISFET formation region; forming gate insulating films, polysilicon film and cap insulating film over the semiconductor substrate, forming a gate electrode in the low breakdown voltage MISFET formation region and high breakdown voltage MISFET formation region, and then forming a gate electrode in a memory cell formation region. By the manufacturing technology of a semiconductor device for forming the gate electrodes of a first MISFET and a second MISFET in different steps, the present invention makes it possible to provide the first MISFET and the second MISFET each having improved reliability.

Abstract: The performance of a semiconductor device including a nonvolatile memory is enhanced. Each of nonvolatile memory cells arranged over a silicon substrate includes: a first n-well; a second n-well formed in a place different from the place thereof; a selection transistor formed in the first n-well; and an electric charge storage portion having a floating gate electrode and a storage portion p-well. The floating gate electrode is so placed that it overlaps with part of the first n-well and the second n-well. The storage portion p-well is placed in the first n-well so that it partly overlaps with the floating gate electrode. In this nonvolatile memory cell, memory information is erased by applying positive voltage to the second n-well to discharge electrons in the floating gate electrode to the second n-well.

Abstract: An apparatus for a user to interface with a control object apparatus by a posture or a motion of the user's physical part. An image input unit inputs an image including the user's physical part. A gesture recognition unit recognizes the posture or the motion of the user's physical part from the image. A control unit controls the control object apparatus based on an indication corresponding to the posture or the motion. A gesture information display unit displays an exemplary image of the posture or the motion recognized for the user's reference to indicate the control object apparatus.

Abstract: There is provided a technology capable of improving the processing precision of memory cells forming a nonvolatile memory in a semiconductor device including the nonvolatile memory. A second polysilicon film is formed in such a manner as to cover a first polysilicon film and a dummy gate electrode. Thus, the second polysilicon film is formed reflecting the shapes of a step difference portion and a gap groove. Particularly, in the second polysilicon film covering the gap groove, a concave part is formed. Subsequently, over the second polysilicon film, an antireflection film is formed. Thus, the antireflection film having high flowability flows from the higher region to the lower region of the step difference portion, but is stored in a sufficient amount in the concave part. Accordingly, the antireflection film is supplied from the concave part so as to compensate for the amount of the antireflection film to flow out therefrom.

Abstract: The semiconductor device has: a first magnetoresistance element; a second magnetoresistance element. The first and second magnetoresistance elements each includes a free layer which can be changed in spin orientation therein and a pinned layer which is fixed in spin orientation therein. The first magnetoresistance element is coupled to a first transistor at the free layer, and to a first power-source terminal at the pinned layer. The second magnetoresistance element is coupled to a second transistor at the free layer, and to the first power-source terminal at the pinned layer. In this device, the reliability of stored data is increased by preventing an undesired resistance condition's change in a magnetoresistance memory cell.

Abstract: Provided is a manufacturing method of a semiconductor device, which comprises forming a film stack of a gate insulating film, a charge storage film, insulating film, polysilicon film, silicon oxide film, silicon nitride film and cap insulating film over a semiconductor substrate; removing the film stack by photolithography and etching from a low breakdown voltage MISFET formation region and a high breakdown voltage MISFET formation region; forming gate insulating films, polysilicon film and cap insulating film over the semiconductor substrate, forming a gate electrode in the low breakdown voltage MISFET formation region and high breakdown voltage MISFET formation region, and then forming a gate electrode in a memory cell formation region. By the manufacturing technology of a semiconductor device for forming the gate electrodes of a first MISFET and a second MISFET in different steps, the present invention makes it possible to provide the first MISFET and the second MISFET each having improved reliability.