Patents by Inventor Yasuhiro Teraoka

Yasuhiro Teraoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240065645
    Abstract: Systems and methods are described, which generate a plurality of virtual monochromatic X-ray images having different energy levels even with a CT system with single energy CT. An example CT system includes an X-ray tube in which a prescribed tube voltage (120 (kVp)) is applied and one or more processors. The one or more processors perform an operation including inputting a CT image generated based on the single energy CT data collected from a subject body to a trained neural network (94), and causing the trained neural network to infer 40 (keV), 50 (keV), 60 (keV), 80 (keV), 90 (keV), and 100 (keV) virtual monochromatic X-ray images based on the CT image.
    Type: Application
    Filed: August 28, 2023
    Publication date: February 29, 2024
    Inventors: Miyo Hattori, Yuri Teraoka, Ayako Matsumi, Yasuhiro Imai, Yuhei Koike
  • Publication number: 20240070861
    Abstract: A device including one or more processor for performing an operation, the operation including inputting a CT image into a first trained neural network, causing the first trained neural network to infer a virtual monochromatic X-ray image based on the CT image, generating a water density image and iodine density image based on the CT image and the virtual monochromatic X-ray image inferred by the first trained neural network, inputting the water density image and iodine density image into a second trained neural network, and causing the second trained neural network to infer a water density image and iodine density image based on the water density image and iodine density image.
    Type: Application
    Filed: August 29, 2023
    Publication date: February 29, 2024
    Inventors: Yasuhiro Imai, Yuri Teraoka, Ayako Matsumi
  • Patent number: 5166099
    Abstract: A manufacturing method for a semiconductor device in which an electrode of a semiconductor chip is electrically connected to an inner lead of a carrier tape. The electrodes of the semiconductor chip are brought into contact with the inner lead of the carrier tape. Bonding is performed with inner lead droop controlled to no more than 80 .mu.m.
    Type: Grant
    Filed: September 13, 1991
    Date of Patent: November 24, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tetsuya Ueda, Osami Nakagawa, Haruo Shimamoto, Yasuhiro Teraoka, Seiji Takemura
  • Patent number: 5157478
    Abstract: A packaged semiconductor device includes an insulating film having an opening, a semiconductor chip disposed in the opening of the insulating film and having a plurality of electrodes, a plurality of leads, each having one end connected to a corresponding electrode, the plurality of leads being supported on the insulating film, a heat radiator disposed opposite and spaced from the semiconductor chip, and a resin package body encapsulating the semiconductor chip and part of the heat radiator, leaving a surface of the heat radiator externally exposed and the second ends of the plurality of leads extending outwardly from the package.
    Type: Grant
    Filed: December 18, 1991
    Date of Patent: October 20, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tetsuya Ueda, Haruo Shimamoto, Yasuhiro Teraoka, Hideya Yagoura, Hiroshi Seki
  • Patent number: 5064706
    Abstract: A carrier tape includes a film having an opening for receiving a semiconductor chip to be resin-molded by a pair of mold halves and outer lead holes formed around the periphery of the opening, a plurality of leads for mounting the semiconductor chip on the film, and a resin running portion cooperating, when the mold halves are closed with the film held between the mold halves, with a gate formed on a parting surface of one of the mold halves to define a resin running path which extends from a portion of the film outside the outer lead holes to the opening for guiding a molten resin into the mold halves while preventing the resin from entering the outer lead holes.
    Type: Grant
    Filed: December 8, 1988
    Date of Patent: November 12, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tetsuya Ueda, Haruo Shimamoto, Hideya Yagoura, Hiroshi Seki, Yasuhiro Teraoka
  • Patent number: 4839713
    Abstract: A package structure comprising a metallic cap having a bottom wall to which the bottom surface of the semiconductor chip is electrically and mechanically connected, a side wall extending from said bottom wall and surrounding the semiconductor chip, and a flange extending outwardly from said side wall substantially parallel to said bottom wall, said flange supporting the lead conductors thereon through an electrically insulating material. The electrical connection means is disposed between the metallic cap flange and the lead conductor for establishing an electrical connection therebetween. The electrical connection means may comprise an electrically conductive projection formed on the flange of the metal cap, extending through a notch in the insulating material and electrically connected to the lead conductor.
    Type: Grant
    Filed: February 17, 1988
    Date of Patent: June 13, 1989
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuhiro Teraoka, Tetsuya Ueda, Hideya Yagoura, Haruo Shimamoto, Shigeyuki Nango, Toshinobu Banjo, Hiroshi Seki