Abstract: An electroless gold plating solution with which one or more openings formed in a resist overlying a substrate can be filled in a short time, the openings having a width on the order of micrometer, in particular, 100 ?m or smaller, in terms of the width of the exposed substrate area, and having a height of 3 ?m or larger. The electroless gold plating solution contains a deposition accelerator for deposition in fine areas, and a microfine pattern of 100 ?m or finer is formed therefrom.

Abstract: An electrode connection structure of a semiconductor chip is provided to realize a highly reliable electrical connection with low stress without using a bump. A conductive member may be used for such an electrode connection structure. A semiconductor device is provided wherein semiconductor chips are arranged in layers without providing the semiconductor chips with a through via, and a method is provided for manufacturing such a semiconductor device. A part or all of the surface of a horizontal recess, which is formed in an adhesive layer arranged between a first electrode of a lower layer and a second electrode of an upper layer, is provided with a conductive member for connecting the first electrode and the second electrode.

Abstract: An electrode connection structure of a semiconductor chip is provided to realize a highly reliable electrical connection with low stress without using a bump. A conductive member may be used for such an electrode connection structure. A semiconductor device is provided wherein semiconductor chips are arranged in layers without providing the semiconductor chips with a through via, and a method is provided for manufacturing such a semiconductor device. A part or all of the surface of a horizontal recess, which is formed in an adhesive layer arranged between a first electrode of a lower layer and a second electrode of an upper layer, is provided with a conductive member for connecting the first electrode and the second electrode.

Abstract: A semiconductor device is made up of an organic substrate; through vias which penetrate the organic substrate in its thickness direction; external electrodes and internal electrodes provided to the front and back faces of the organic substrate and electrically connected to the through vias; a semiconductor element mounted on one main surface of the organic substrate via a bonding layer, with an element circuit surface thereof facing upward; an insulating material layer for sealing the semiconductor element and a periphery thereof; a metal thin film wiring layer provided in the insulating material layer, with a part of this metal thin film wiring layer being exposed on an external surface; metal vias provided in the insulating material layer and electrically connected to the metal thin film wiring layer; and external electrodes formed on the metal thin film wiring layer.

Abstract: An electroless gold plating solution with which one or more openings formed in a resist overlying a substrate can be filled in a short time, the openings having a width on the order of micrometer, in particular, 100 ?m or smaller, in terms of the width of the exposed substrate area, and having a height of 3 ?m or larger. The electroless gold plating solution contains a deposition accelerator for deposition in fine areas, and a microfine pattern of 100 ?m or finer is formed therefrom.

Abstract: An electrode connection structure of a semiconductor chip is provided to realize a highly reliable electrical connection with low stress without using a bump. A conductive member may be used for such an electrode connection structure. A semiconductor device is provided wherein semiconductor chips are arranged in layers without providing the semiconductor chips with a through via, and a method is provided for manufacturing such a semiconductor device. A part or all of the surface of a horizontal recess, which is formed in an adhesive layer arranged between a first electrode of a lower layer and a second electrode of an upper layer, is provided with a conductive member for connecting the first electrode and the second electrode.

Abstract: An electrode connection structure of a semiconductor chip is provided to realize a highly reliable electrical connection with low stress without using a bump. A conductive member may be used for such an electrode connection structure. A semiconductor device is provided wherein semiconductor chips are arranged in layers without providing the semiconductor chips with a through via, and a method is provided for manufacturing such a semiconductor device. A part or all of the surface of a horizontal recess, which is formed in an adhesive layer arranged between a first electrode of a lower layer and a second electrode of an upper layer, is provided with a conductive member for connecting the first electrode and the second electrode.

Abstract: Semiconductor chips are stacked on a first main surface of an interconnect substrate. The semiconductor chips have a base and connection bumps. Mutually facing two of the bases and the interconnect substrate are apart from each other. The connection bumps electrically connect the mutually facing two of the bases and the interconnect substrate together. Insulating sealing members seal the connection bumps and fill spaces between the mutually facing two of the base and the interconnect substrate. The sealing members have a cavity penetrating the sealing member.

Abstract: Semiconductor chips are stacked on a first main surface of an interconnect substrate. The semiconductor chips have a base and connection bumps. Mutually facing two of the bases and the interconnect substrate are apart from each other. The connection bumps electrically connect the mutually facing two of the bases and the interconnect substrate together. Insulating sealing members seal the connection bumps and fill spaces between the mutually facing two of the base and the interconnect substrate. The sealing members have a cavity penetrating the sealing member.

Abstract: A plurality of semiconductor chips bent along the outer circumferential surface of a cylindrical substrate are mounted to the outer circumferential surface of the substrate. The bumps of these semiconductor chips are connected to connection pads formed on the outer circumferential surface of the substrate. By diminishing the curvature radius of the bent semiconductor chips, the size of the semiconductor module can be made smaller than the size of the chip.

Abstract: A plurality of semiconductor chips bent along the outer circumferential surface of a cylindrical substrate are mounted to the outer circumferential surface of the substrate. The bumps of these semiconductor chips are connected to connection pads formed on the outer circumferential surface of the substrate. By diminishing the curvature radius of the bent semiconductor chips, the size of the semiconductor module can be made smaller than the size of the chip.

Abstract: Resin meltable at a time of reflowing is provided on the surface of a semiconductor chip and top ends of the connection electrodes are located parallel with the surface of the resin. A semiconductor chip is mounted on a mounting substrate and, upon reflowing, the resin is molten to allow the semiconductive chip to be bonded to the mounting substrate and encapsulate a resultant structure.

Abstract: In this manufacturing method of a semiconductor device, after an electrode pad is formed on a surface of a semiconductor substrate, on this surface where the electrode pad is formed, except for on the electrode pad an insulating protective film is formed, then a layer of barrier metal covering the electrode pad is formed. Subsequently, a covering layer of curable resin having a hole exposing at least a part of the layer of barrier metal is formed on a semiconductor substrate. Then, the hole of the covering layer of curable resin is filled by conductive material and on the filled portion a protrusion is formed. Finally, these filled and protruded portions are exposed to heat treatment to form a protruded electrode for external connection. Thus, a semiconductor device having a protruded electrode that is high sufficiently, can be manufactured. Thermal stress does not concentrate at joint portion with the semiconductor substrate, and semiconductor device is highly reliable.

Abstract: Resin meltable at a time of reflowing is provided on the surface of a semiconductor chip and top ends of the connection electrodes are located parallel with the surface of the resin. A semiconductor chip is mounted on a mounting substrate and, upon reflowing, the resin is molten to allow the semiconductive chip to be bonded to the mounting substrate and encapsulate a resultant structure.

Abstract: A heat sink is attached to a semiconductor element functioning as an exothermic element, which is mounted on a circuit board and has a predetermined allowable power consumption, thereby cooling the semiconductor element. A semiconductor element having a lower allowable power consumption than the semiconductor element having the predetermined power consumption, which is hardly exposed to a cooling air flow cooled via the heat sink, is connected to a heat conductive auxiliary member connected at one end to the heat sink. Thus, the heat radiation efficiency of the semiconductor element having the lower allowable power consumption is enhanced.

Abstract: A heat sink is attached to a semiconductor element functioning as an exothermic element, which is mounted on a circuit board and has a predetermined allowable power consumption, thereby cooling the semiconductor element. A semiconductor element having a lower allowable power consumption than the semiconductor element having the predetermined power consumption, which is hardly exposed to a cooling air flow cooled via the heat sink, is connected to a heat conductive auxiliary member connected at one end to the heat sink. Thus, the heat radiation efficiency of the semiconductor element having the lower allowable power consumption is enhanced.

Abstract: In a semiconductor device and a method for manufacturing the same according to the present invention, a bonding wire is bonded to an electrode pad of a semiconductor element by ball bonding. The bonding wire is cut to have a predetermined length, and compressed and crushed into a bump. By doing so, a wire bump electrode is formed on each electrode pad of the semiconductor element. The wire bump electrodes formed on the electrode pads are then bonded to the respective substrate electrodes on a mounting substrate by melting a low-melting metal. As a result, a flip chip bonding structure wherein the semiconductor element and mounting substrate are bonded to each other by the wire bump electrodes, is obtained.

Abstract: Since an electronic device comprises an electronic component, an external connection terminal electrically connected to the electronic component, and an envelope for sealing the electronic part and having a thickness less than about 0.5 mm, the electronic device is miniaturized even in the case where it is provided with a large number of terminals. Further, since the electronic component is sealed by the envelope, moisture, etc. is not admitted into the electronic component, resulting in high reliability. In addition, since the thickness of the envelope is thin, the external terminal can be shortened. Thus, the inductance or capacitance of this terminal can be reduced.

Abstract: A semiconductor chip is packaged within film carriers which serve as the enclosure of the semiconductor chip. The finished semiconductor device is flexible, bendable, and very thin. In manufacturing this semiconductor device, the process of laminating film carriers, the process of electrically connecting the semiconductor chip and film carriers, and the process of sealing the semiconductor chip, can be performed at the same time, shortening the manufacturing time and reducing manufacturing cost.

Abstract: The present invention comprises a semiconductor chip 1, chip electrodes 2 provided on one surface of the semiconductor chip 1, and connected to semiconductor elements formed in the semiconductor chip, a flexible insulating film 3 wrapping the chip electrodes, wiring layers 5 formed in the insulating film 3, and electrically connected to the chip electrodes 2, and terminal electrodes 6 provided on that surface of the insulating film 3 which extends on the upper surface of the chip 1, the electrodes 6 being electrically connected to the wiring layers 5, and functioning as external terminals of the chip 1. Thus, the terminal electrodes 6 are introduced, by means of the wiring layers 5 formed in the insulating film 3, onto that surface of the insulating film 3 which extends on the upper surface of the chip 1.