Abstract: A mixing apparatus which prevents erosion of left and right side walls 12a 12b for a flow path 12 for a molten substance of high temperature M and homogenizes the molten substance of high temperature while occurrence of air bubbles is prevented, wherein there are a plurality of mixing units 11 in the flow path 12; an even number of pairs of mixing units 11 are arranged symmetrically with respect to the center line in a longitudinal direction of the flow path 12 and the gap s between a left side wall or a right side wall and an outer peripheral edge of a mixing blade 14 is determined to be 0.04-0.1 times as much as the distance W between the left and right side walls 12a, 12b.

Abstract: Four gate electrodes of an n-type basic cell of a gate array are essentially oriented in a circular tangential direction of a radius relative to the center point Q of a cell. The electrodes have an upper and lower and a right and left symmetrical layout arrangement relative to the cell upper and lower center line and left and right center line. As a consequence, adjacent gate electrodes are positioned in a .+-.90.degree. rotating symmetry. Each gate electrode has wiring connection areas on both ends. The wiring connection areas overlap the pre-rotation wiring connection areas by a .+-.90.degree. rotation of the cell. Because the gate electrodes are essentially oriented along the circumference direction, the source and the drain are separated in the radial direction of the center of the cell. The wiring connection areas are not concentrated at the center of the cell, and this improves the wiring capabilities within the cell.

Abstract: An output current varying circuit 10 includes a control signal generating circuit 12, an output current supplying circuit 14 and an output terminal 16. Circuit 12 receives an output signal Sout of a dedicated logic circuit 11, and an output signal S1 from a predetermined circuit or an external signal S2 from an input terminal 13, and generates first and second control signals C1 and C2. Circuit 14 is constituted by two P-channel MIS transistors Tr1 and Tr2 connected in parallel between high potential Vdd and output terminal 16. When output signal Sout from logic circuit 11 is at H level, transistor Tr2 is in an on state and an output current i at H level appears on output terminal 16. When output signal Sout is a L level and a current value changing signal S is at L level, transistors Tr1 and Tr2 are both in an off state and the output current is zero.

Abstract: In a master slice integrated circuit device composed of an array of internal cells having contact members, an array of external cells having contact members and formed outwardly from the internal cell array, a main power circuit region formed on the external cell array, a plurality of power lines formed on the internal array region, and a plurality of signal lines for electrically interconnecting selected contact members of the internal and external cells, intermediate power line connection regions are provided to conductively connect each power line to the main power circuit region, the intermediate connection regions including, for each power line, a power branch-off member disposed at a given position on the main power circuit region and extending substantially in the direction of its respective power line, and a connection allowance member intersecting, and connected to, the power branch-off member and having a predetermined length, the connection allowance member being conductively connected between its

Abstract: Disclosed is a semiconductor device having complementary metal insulator semiconductor field-effect transistors (MISFETs) in which a plurality of basic cells having N-channel MOSs and P-channel MOSs are disposed. In this semiconductor device, a sub MISFET is disposed adjacently to a stopper layer in a region adjacent to other basic cell. An element such as a transmission gate composed of a single element can be actualized by use of the sub-MISFET. In the semiconductor device of this invention, a working efficiency thereof is improved. A response velocity of the P-channel MOS can also be improved using the sub-MISFET. A numerical quantity of the basic cells constituting a circuit can be reduced, resulting in a reduction in parasitic capacity. An operating time of the circuit is thereby decreased.

Abstract: In a master slice integrated circuit device composed of an array of internal cells having contact members, an array of external cells having contact members and formed outwardly from the internal cell array, a main power circuit region formed on the external cell array, a plurality of power lines formed on the internal array region, and a plurality of signal lines for electrically interconnecting selected contact members of the internal and external cells, intermediate power line connection regions are provided to conductively connect each power line to the main power circuit region, the intermediate connection regions including, for each power line, a power branch-off member disposed at a given position on the main power circuit region and extending substantially in the direction of its respective power line, and a connection allowance member intersecting, and connected to, the power branch-off member and having a predetermined length, the connection allowance member being conductively connected between its

Abstract: A semiconductor device assembly composed of a plurality of unit semiconductor devices formed into a logic circuit by selective connection among elements in the unit devices and among the unit devices. Each of the unit devices includes at least a first insulated-gate type field-effect transistor of a first conductivity type and a second insulated-gate type field-effect transistor of a second conductivity type which is disposed adjacent to the first transistor and has a gate electrode separated from a gate electrode of the first transistor. The gate electrodes of the respective transistors have at least a gate terminal portion at the side adjacent to each other, and the gate terminal portion of the first field-effect transistor has at least a first wire connecting location and a second wire connecting location. By using the second wire connecting location, wiring in and among the unit devices can be carried out via the shortest aluminum wires of a first layer, so that the wiring feasibility can be enhanced.