Abstract: A recording interruption-controlling section interrupts recording if vibration is detected in order to complete proper recording by making it possible to interrupt and restart recording in cases where proper recording is difficult to continue because of vibration or the like. A recording quality-confirming section reproduce a recording signal after the recording has been interrupted and detects a recording location at which degradation in recording quality occurs. A CD-ROM encoder or a CD encoder re-encodes data held in a buffer, and recording is restarted from the location at which degradation in recording quality occurs under the control of a recording restart-controlling section.

Abstract: When data recording is interrupted, a location at which data have been last recorded is accurately detected and a seamless restart of the recording is achieved even if reproducing errors occur due to scratches or the like on an optical disk. A pattern data that indicates a pit pattern of data to be recorded or having been recorded is compared to a pattern data that is reproduced within a predetermined range (window) of clock cycles, and when a match is obtained, a recording restart signal is output to restart the recording operation.

Abstract: A control information generating circuit uses linear velocity information at a recording/reproduction position on an optical disc, which is obtained from an information recording medium by a synchronous signal cycle counter, and revolution number information, which is obtained from a rotation mechanism by a cycle counter of a frequency generator, to generate a piece of rotation control information, and the resultant information is supplied to a motor driving circuit. A variation detecting circuit generates a linear velocity abnormality detecting signal based on an abnormality detection result obtained by a division circuit, thereby preventing an abnormal operation of a spindle motor. With such a structure, switching of the control mode between CAV control mode and CLV control mode in a continuous recording/reproduction operation on an optical disc, or the like, is smoothly performed using one pierce of rotation control information.

Abstract: In the case where a data recording operation is suspended, even when a synchronization pattern cannot be detected due to a scratch of an optical disk or the like, a position where the last data is recorded is precisely detected so as to resume the recording operation without causing a joint. For this purpose, in resuming the suspended recording operation in the data recording device of this invention, reproducing pattern data corresponding to a pit pattern having been recorded in the optical disk is first reproduced. A synchronization pattern detection circuit detects a synchronization pattern and outputs a pre-complementation synchronization signal. A synchronization signal complementation circuit detects presence of a synchronization signal (synchronization signal pulse) and outputs a detection/loss signal to a synchronization signal non-detection counter.

Abstract: A recording interruption-controlling section interrupts recording if vibration is detected in order to complete proper recording by making it possible to interrupt and restart recording in cases where proper recording is difficult to continue because of vibration or the like. A recording quality-confirming section reproduce a recording signal after the recording has been interrupted and detects a recording location at which degradation in recording quality occurs. A CD-ROM encoder or a CD encoder re-encodes data held in a buffer, and recording is restarted from the location at which degradation in recording quality occurs under the control of a recording restart-controlling section.

Abstract: When data recording is interrupted, a location at which data have been last recorded is accurately detected and a seamless restart of the recording is achieved even if reproducing errors occur due to scratches or the like on an optical disk. A pattern data that indicates a pit pattern of data to be recorded or having been recorded is compared to a pattern data that is reproduced within a predetermined range (window) of clock cycles, and when a match is obtained, a recording restart signal is output to restart the recording operation.

Abstract: A disk reproducing device comprising: clock signal extracting means for extracting a regenerative clock signal from a reproduced signal; synchronization detecting means for detecting a synchronizing signal from the reproduced signal; extracted clock signal verification means for verifying that the regenerative clock signal is correctly extracted; signal processing means for performing variable linear velocity reproduction; target reproducing speed setting means for setting a target reproducing speed; reproducing speed verification means for verifying that a reproducing speed reaches the target reproducing speed; and signal processing start command generating means for outputting a signal processing start command referring outputs of said extracted clock signal verification means and said reproducing speed verification means.

Abstract: A disk reproducing device comprising: clock signal extracting means for extracting a regenerative clock signal from a reproduced signal; synchronization detecting means for detecting a synchronizing signal from the reproduced signal; extracted clock signal verification means for verifying that the regenerative clock signal is correctly extracted; signal processing means for performing variable linear velocity reproduction; target reproducing speed setting means for setting a target reproducing speed; reproducing speed verification means for verifying that a reproducing speed reaches the target reproducing speed; and signal processing start command generating means for outputting a signal processing start command referring outputs of said extracted clock signal verification means and said reproducing speed verification means.

Abstract: A disk reproducing device comprising: clock signal extracting means for extracting a regenerative clock signal from a reproduced signal; synchronization detecting means for detecting a synchronizing signal from the reproduced signal; extracted clock signal verification means for verifying that the regenerative clock signal is correctly extracted; signal processing means for performing variable linear velocity reproduction; target reproducing speed setting means for setting a target reproducing speed; reproducing speed verification means for verifying that a reproducing speed reaches the target reproducing speed; and signal processing start command generating means for outputting a signal processing start command referring outputs of said extracted clock signal verification means and said reproducing speed verification means.

Abstract: A virtual RAM read address generating circuit (41) generates a virtual address on the basis of an output signal of a crystal oscillation circuit (36). A phase comparison circuit (39) which performs phase comparison with a write address, and a spindle control circuit (3) which controls rotation of a disk with reference to outputs of a frequency comparison circuit (38) and the phase comparison circuit (39) are disposed. Therefore, a phase error can be fed back to a spindle motor, thereby preventing linear velocity deviation from occurring in a steady state. By using the thus configured reproducing device, the reproduction quality in the case where a disk wherein recording was performed by the CLV system is reproduced by the variable linear velocity reproduction system is ensured, and both high-speed access and low power consumption are realized.

Abstract: A disk reproducing device comprising: clock signal extracting means for extracting a regenerative clock signal from a reproduced signal; synchronization detecting means for detecting a synchronizing signal from the reproduced signal; extracted clock signal verification means for verifying that the regenerative clock signal is correctly extracted; signal processing means for performing variable linear velocity reproduction; target reproducing speed setting means for setting a target reproducing speed; reproducing speed verification means for verifying that a reproducing speed reaches the target reproducing speed; and signal processing start command generating means for outputting a signal processing start command referring outputs of said extracted clock signal verification means and said reproducing speed verification means.

Abstract: A virtual RAM read address generating circuit (41) generates a virtual address-on the basis of an output signal of a crystal oscillation circuit (36). A phase comparison circuit (39) which performs phase comparison with a write address, and a spindle control circuit (3) which controls rotation of a disk with reference to outputs of a frequency comparison circuit (38) and the phase comparison circuit (39) are disposed. Therefore, a phase error can be fed back to a spindle motor, thereby preventing linear velocity deviation from occurring in a steady state. By using the thus configured reproducing device, the reproduction quality in the case where a disk wherein recording was performed by the CLV system is reproduced by the variable linear velocity reproduction system is ensured, and both high-speed access and low power consumption are realized.

Abstract: A virtual RAM read address generating circuit (41) generates a virtual address on the basis of an output signal of a crystal oscillation circuit (36). A phase comparison circuit (39) which performs phase comparison with a write address, and a spindle control circuit (3) which controls rotation of a disk with reference to outputs of a frequency comparison circuit (38) and the phase comparison circuit (39) are disposed. Therefore, a phase error can be fed back to a spindle motor, thereby preventing linear velocity deviation from occurring in a steady state. By using the thus configured reproducing device, the reproduction quality in the case where a disk wherein recording was performed by the CLV system is reproduced by the variable linear velocity reproduction system is ensured, and both high-speed access and low power consumption are realized.