Patents by Inventor Yasuhisa SHINTOKU
Yasuhisa SHINTOKU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11705442Abstract: According to one embodiment, a semiconductor device includes an integrated circuit (IC) chip and a silicon capacitor. The IC chip has a first terminal and a second terminal on a first surface. The silicon capacitor has a first electrode and a second electrode on a second surface facing the first surface. The first electrode is electrically connected to the first terminal through a first conductive member, and the second electrode is electrically connected to the second terminal through a second conductive member.Type: GrantFiled: March 3, 2021Date of Patent: July 18, 2023Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Atsushi Hosokawa, Yasuhisa Shintoku, Yasukazu Noine, Yoshiharu Katayama
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Publication number: 20220084995Abstract: According to one embodiment, a semiconductor device includes an integrated circuit (IC) chip and a silicon capacitor. The IC chip has a first terminal and a second terminal on a first surface. The silicon capacitor has a first electrode and a second electrode on a second surface facing the first surface. The first electrode is electrically connected to the first terminal through a first conductive member, and the second electrode is electrically connected to the second terminal through a second conductive member.Type: ApplicationFiled: March 3, 2021Publication date: March 17, 2022Inventors: Atsushi HOSOKAWA, Yasuhisa SHINTOKU, Yasukazu NOINE, Yoshiharu KATAYAMA
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Patent number: 11264313Abstract: A semiconductor device includes a molded body and an interconnection layer. The molded body includes a semiconductor chip, at least one terminal body disposed around the semiconductor chip and a resin member provided between the semiconductor chip and the terminal body. The molded body has a first surface, a second surface opposite to the first surface and a side surface connected to the first and second surfaces. The interconnection layer is provided on the first surface of the molded body. The interconnection layer includes an interconnect electrically connecting the semiconductor chip and the terminal body. The terminal body has first and second contact surfaces. The first contact surface is exposed at the first or second surface of the molded body. The second contact surface is connected to the first contact surface and exposed at the side surface of the molded body.Type: GrantFiled: February 1, 2019Date of Patent: March 1, 2022Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Akito Shimizu, Yasuhisa Shintoku, Yoshihisa Imori, Hiroaki Kishi, Atsushi Hosokawa, Tomohiko Imada, Shinya Shimamura
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Publication number: 20200083150Abstract: A semiconductor device includes a molded body and an interconnection layer. The molded body includes a semiconductor chip, at least one terminal body disposed around the semiconductor chip and a resin member provided between the semiconductor chip and the terminal body. The molded body has a first surface, a second surface opposite to the first surface and a side surface connected to the first and second surfaces. The interconnection layer is provided on the first surface of the molded body. The interconnection layer includes an interconnect electrically connecting the semiconductor chip and the terminal body. The terminal body has first and second contact surfaces. The first contact surface is exposed at the first or second surface of the molded body. The second contact surface is connected to the first contact surface and exposed at the side surface of the molded body.Type: ApplicationFiled: February 1, 2019Publication date: March 12, 2020Inventors: Akito Shimizu, Yasuhisa Shintoku, Yoshihisa Imori, Hiroaki Kishi, Atsushi Hosokawa, Tomohiko Imada, Shinya Shimamura
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Patent number: 10490485Abstract: A semiconductor device that includes a first die pad, an adhesive, and a second die pad fixed to the top surface of the first die pad via the adhesive. The second die pad includes a body portion and a protrusion portion provided on a side surface of the body portion. A semiconductor chip is fixed to a top surface of the second die pad, and a lead is electrically connected to the semiconductor chip. The semiconductor device further includes a package material that covers the first die pad, the second die pad, the semiconductor chip, and the lead. The first die pad is substantially as thick as the lead.Type: GrantFiled: June 20, 2018Date of Patent: November 26, 2019Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Naohisa Okumura, Yasuhisa Shintoku, Tetsuya Kurosawa, Hiroaki Kishi
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Publication number: 20180331019Abstract: A semiconductor device that includes a first die pad, an adhesive, and a second die pad fixed to the top surface of the first die pad via the adhesive. The second die pad includes a body portion and a protrusion portion provided on a side surface of the body portion. A semiconductor chip is fixed to a top surface of the second die pad, and a lead is electrically connected to the semiconductor chip. The semiconductor device further includes a package material that covers the first die pad, the second die pad, the semiconductor chip, and the lead. The first die pad is substantially as thick as the lead.Type: ApplicationFiled: June 20, 2018Publication date: November 15, 2018Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Naohisa OKUMURA, Yasuhisa SHINTOKU, Tetsuya KUROSAWA, Hiroaki KISHI
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Patent number: 10026677Abstract: A semiconductor device that includes a first die pad, an adhesive, and a second die pad fixed to the top surface of the first die pad via the adhesive. The second die pad includes a body portion and a protrusion portion provided on a side surface of the body portion. A semiconductor chip is fixed to a top surface of the second die pad, and a lead is electrically connected to the semiconductor chip. The semiconductor device further includes a package material that covers the first die pad, the second die pad, the semiconductor chip, and the lead. The first die pad is substantially as thick as the lead.Type: GrantFiled: August 31, 2016Date of Patent: July 17, 2018Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Naohisa Okumura, Yasuhisa Shintoku, Tetsuya Kurosawa, Hiroaki Kishi
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Publication number: 20170250124Abstract: A semiconductor device that includes a first die pad, an adhesive, and a second die pad fixed to the top surface of the first die pad via the adhesive. The second die pad includes a body portion and a protrusion portion provided on a side surface of the body portion. A semiconductor chip is fixed to a top surface of the second die pad, and a lead is electrically connected to the semiconductor chip. The semiconductor device further includes a package material that covers the first die pad, the second die pad, the semiconductor chip, and the lead. The first die pad is substantially as thick as the lead.Type: ApplicationFiled: August 31, 2016Publication date: August 31, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Naohisa OKUMURA, Yasuhisa SHINTOKU, Tetsuya KUROSAWA, Hiroaki KISHI